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參數(shù)資料
| 型號： | A54SX08P-3TQ208M |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | FPGA |
| 英文描述： | 54SX Family FPGAs |
| 中文描述： | 54SX家庭的FPGA |
| 文件頁數(shù)： | 6/57頁 |
| 文件大?。?/td> | 415K |
| 代理商： | A54SX08P-3TQ208M |
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5 4 S X F a m ily F P G A s
6
v3.1
R out ing R e s ourc e s
Clusters and SuperClusters can be connected through the
use of two innovative local routing resources called
FastConnect
and
DirectConnect,
which enable extremely
fast and predictable interconnection of modules within
Clusters and SuperClusters (
Figure5
and
Figure6 on
page7
). This routing architecture also dramatically reduces
the number of antifuses required to complete a circuit,
ensuring the highest possible performance.
DirectConnect is a horizontal routing resource that provides
connections from a C-cell to its neighboring R-cell in a given
SuperCluster. DirectConnect uses a hard-wired signal path
requiring no programmable interconnection to achieve its
fast signal propagation time of less than 0.1 ns.
FastConnect enables horizontal routing between any two
logic modules within a given SuperCluster and vertical
routing with the SuperCluster immediately below it. Only
one programmable connection is used in a FastConnect
path, delivering maximum pin-to-pin propagation of 0.4 ns.
In addition to DirectConnect and FastConnect, the
architecture makes use of two globally oriented routing
resources known as segmented routing and high-drive
routing. Actel’s segmented routing structure provides a
variety of track lengths for extremely fast routing between
SuperClusters. The exact combination of track lengths and
antifuses within each path is chosen by the 100percent
automatic place and route software to minimize signal
propagation delays.
Actel’s high-drive routing structure provides three clock
networks. The first clock, called HCLK, is hard wired from
the HCLK buffer to the clock select MUX in each R-cell. This
provides a fast propagation path for the clock signal,
enabling the 3.7 ns clock-to-out (pin-to-pin) performance of
the SX devices. The hard-wired clock is tuned to provide
clock skew as low as 0.25 ns. The remaining two clocks
(CLKA, CLKB) are global clocks that can be sourced from
external pins or from internal logic signals within the SX
device.
Figure 4
Cluster Organization
Type 1 SuperCluster
Type 2 SuperCluster
Cluster 1
Cluster 2
Cluster 2
Cluster 1
R-Cell
C-Cell
D0
D1
D2
D3
DB
A0
B0
A1
B1
Sa
Sb
Y
Direct
Connect
Input
CLKA,
CLKB,
Internal Logic
HCLK
CKS
CKP
CLRB
PSETB
Y
D
Q
Routed
Data Input
S0
S1
相關PDF資料 |
PDF描述 |
|---|---|
| A54SX08P-3TQ208PP | 54SX Family FPGAs |
| A54SX08P-3VQ208 | 54SX Family FPGAs |
| A54SX16 | Quad 2-input positive-NAND gates 14-SO 0 to 70 |
| A54SX32 | Quad 2-input positive-NAND gates 8-SO 0 to 70 |
| A54SX32-1BG208I | Quad 2-input positive-NAND gates 8-SO 0 to 70 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| A54SX08P-3TQ208PP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:54SX Family FPGAs |
| A54SX08P-3TQG208 | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:SX Family FPGAs |
| A54SX08-P-3TQG208I | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:SX Family FPGAs |
| A54SX08P-3TQG208I | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:SX Family FPGAs |
| A54SX08-P-3TQG208M | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:SX Family FPGAs |
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