Table 1-7 A54SX16P AC Specifications for (PCI Operation) Symbol Para" />
參數(shù)資料
型號(hào)： A54SX16-CQ208B
廠商： Microsemi SoC
文件頁(yè)數(shù)： 6/64頁(yè)
文件大?。?/td> 0K
描述： IC FPGA SX 24K GATES 208-CQFP
標(biāo)準(zhǔn)包裝： 1
系列： SX
LAB/CLB數(shù)： 1452
輸入/輸出數(shù)： 175
門(mén)數(shù)： 24000
電源電壓： 3 V ~ 3.6 V，4.75 V ~ 5.25 V
安裝類(lèi)型： 表面貼裝
封裝/外殼： 208-BFCQFP，帶拉桿
供應(yīng)商設(shè)備封裝： 208-CQFP（75x75）
SX Family FPGAs
1- 10
v3.2
A54SX16P AC Specifications for (PCI Operation)
Table 1-7
A54SX16P AC Specifications for (PCI Operation)
Symbol
Parameter
Condition
Min.
Max.
Units
IOH(AC)
Switching Current High
0 < VOUT ≤ 1.4
1
–44
mA
1.4
≤ V
OUT < 2.4
1, 2
–44 + (VOUT – 1.4)/0.024
mA
3.1 < VOUT < VCC
1, 3
(Test Point)
VOUT = 3.1
3
–142
mA
IOL(AC)
Switching Current High
VOUT ≥ 2.2
1
95
mA
2.2 > VOUT > 0.55
1
VOUT/0.023
0.71 > VOUT > 0
1, 3
mA
(Test Point)
VOUT = 0.71
3
206
mA
ICL
Low Clamp Current
–5 < VIN ≤ –1
–25 + (VIN + 1) /0.015
mA
slewR
Output Rise Slew Rate
0.4 V to 2.4 V load4
15
V/ns
slewF
Output Fall Slew Rate
2.4 V to 0.4 V load4
15
V/ns
Notes:
1. Refer to the V/I curves in Figure 1-9 on page 1-11. Switching current characteristics for REQ# and GNT# are permitted to be one half
of that specified here; i.e., half-size output drivers may be used on these signals. This specification does not apply to CLK and RST#,
which are system outputs. “Switching Current High” specifications are not relevant to SERR#, INTA#, INTB#, INTC#, and INTD#,
which are open drain outputs.
2. Note that this segment of the minimum current curve is drawn from the AC drive point directly to the DC drive point rather than
toward the voltage rail (as is done in the pull-down curve). This difference is intended to allow for an optional N-channel pull-up.
3. Maximum current requirements must be met as drivers pull beyond the last step voltage. Equations defining these maximums (A
and B) are provided with the respective diagrams in Figure 1-9 on page 1-11. The equation defined maxima should be met by
design. In order to facilitate component testing, a maximum current test point is defined for each side of the output driver.
4. This parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the instantaneous rate at any
point within the transition range. The specified load (diagram below) is optional; i.e., the designer may elect to meet this parameter
with an unloaded output per revision 2.0 of the PCI Local Bus Specification. However, adherence to both maximum and minimum
parameters is now required (the maximum is no longer simply a guideline). Since adherence to the maximum slew rate was not
required prior to revision 2.1 of the specification, there may be components in the market for some time that have faster edge rates;
therefore, motherboard designers must bear in mind that rise and fall times faster than this specification could occur, and should
ensure that signal integrity modeling accounts for this. Rise slew rate does not apply to open drain outputs.
1/2 in. max.
Pin
Output
Buffer
VCC
10 pF
1 k
Ω
1 k
Ω
相關(guān)PDF資料
PDF描述
EP4SGX110DF29C4 IC STRATIX IV FPGA 110K 780FBGA
93C56A-I/MS IC EEPROM 2KBIT 2MHZ 8MSOP
EP1S60F1020C6N IC STRATIX FPGA 60K LE 1020-FBGA
A54SX32A-1CQ256 IC FPGA SX 48K GATES 256-CQFP
93C56A-I/ST IC EEPROM 2KBIT 2MHZ 8TSSOP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A54SX16-CQ208M 功能描述:IC FPGA SX 24K GATES 208-CQFP RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:SX 標(biāo)準(zhǔn)包裝:1 系列:ProASICPLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):129024 輸入/輸出數(shù):248 門(mén)數(shù):600000 電源電壓:2.3 V ~ 2.7 V 安裝類(lèi)型:表面貼裝 工作溫度:- 封裝/外殼:352-BFCQFP，帶拉桿 供應(yīng)商設(shè)備封裝:352-CQFP（75x75）
A54SX16-CQ256 功能描述:IC FPGA SX 24K GATES 256-CQFP RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:SX 標(biāo)準(zhǔn)包裝:1 系列:ProASICPLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):129024 輸入/輸出數(shù):248 門(mén)數(shù):600000 電源電壓:2.3 V ~ 2.7 V 安裝類(lèi)型:表面貼裝 工作溫度:- 封裝/外殼:352-BFCQFP，帶拉桿 供應(yīng)商設(shè)備封裝:352-CQFP（75x75）
A54SX16-CQ256B 功能描述:IC FPGA SX 24K GATES 256-CQFP RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:SX 標(biāo)準(zhǔn)包裝:1 系列:ProASICPLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):129024 輸入/輸出數(shù):248 門(mén)數(shù):600000 電源電壓:2.3 V ~ 2.7 V 安裝類(lèi)型:表面貼裝 工作溫度:- 封裝/外殼:352-BFCQFP，帶拉桿 供應(yīng)商設(shè)備封裝:352-CQFP（75x75）
A54SX16P-1PQ208 功能描述:IC FPGA SX 24K GATES 208-PQFP RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:SX 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計(jì):- 輸入/輸出數(shù):360 門(mén)數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類(lèi)型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27）
A54SX16P-1PQ208I 功能描述:IC FPGA SX 24K GATES 208-PQFP RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:SX 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門(mén)數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類(lèi)型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23）
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*