Table 1-9 A54SX16P AC Specifications (3.3 V PCI Operation) Symbol P" />
參數(shù)資料
型號(hào)： A54SX32-2BGG329I
廠商： Microsemi SoC
文件頁(yè)數(shù)： 9/64頁(yè)
文件大小： 0K
描述： IC FPGA SX 48K GATES 329-BGA
標(biāo)準(zhǔn)包裝： 27
系列： SX
LAB/CLB數(shù)： 2880
輸入/輸出數(shù)： 249
門(mén)數(shù)： 48000
電源電壓： 3 V ~ 3.6 V，4.75 V ~ 5.25 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 85°C
封裝/外殼： 329-BBGA
供應(yīng)商設(shè)備封裝： 329-PBGA（31x31）
SX Family FPGAs
v3.2
1-13
A54SX16P AC Specifications (3.3 V PCI Operation)
Table 1-9
A54SX16P AC Specifications (3.3 V PCI Operation)
Symbol Parameter
Condition
Min.
Max.
Units
IOH(AC)
Switching Current High
0 < VOUT ≤ 0.3VCC
1
mA
0.3VCC ≤ VOUT < 0.9VCC
1
–12VCC
mA
0.7VCC < VOUT < VCC
1, 2
–17.1 + (VCC – VOUT)
(Test Point)
VOUT = 0.7VCC
2
–32VCC
mA
IOL(AC)
Switching Current High
VCC > VOUT ≥ 0.6VCC
1
mA
0.6VCC > VOUT > 0.1VCC
1
16VCC
mA
0.18VCC > VOUT > 0
1, 2
26.7VOUT
mA
(Test Point)
VOUT = 0.18VCC
2
38VCC
ICL
Low Clamp Current
–3 < VIN ≤ –1
–25 + (VIN + 1)/0.015
mA
ICH
High Clamp Current
–3 < VIN ≤ –1
25 + (VIN – VOUT – 1)/0.015
mA
slewR
Output Rise Slew Rate3
0.2VCC to 0.6VCC load
1
4
V/ns
slewF
Output Fall Slew Rate3
0.6VCC to 0.2VCC load
1
4
V/ns
Notes:
1. Refer to the V/I curves in Figure 1-10 on page 1-14. Switching current characteristics for REQ# and GNT# are permitted to be
one half of that specified here; i.e., half size output drivers may be used on these signals. This specification does not apply to
CLK and RST# which are system outputs. “Switching Current High” specification are not relevant to SERR#, INTA#, INTB#,
INTC#, and INTD# which are open drain outputs.
2. Maximum current requirements must be met as drivers pull beyond the last step voltage. Equations defining these maximums
(C and D) are provided with the respective diagrams in Figure 1-10 on page 1-14. The equation defined maxima should be
met by design. In order to facilitate component testing, a maximum current test point is defined for each side of the output
driver.
3. This parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the instantaneous rate
at any point within the transition range. The specified load (diagram below) is optional; i.e., the designer may elect to meet
this parameter with an unloaded output per the latest revision of the PCI Local Bus Specification. However, adherence to both
maximum and minimum parameters is required (the maximum is no longer simply a guideline). Rise slew rate does not apply
to open drain outputs.
1/2 in. max.
Pin
Output
Buffer
VCC
10 pF
1 k
Ω
1 k
Ω
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