參數(shù)資料
型號(hào)： A54SX32-3TQ176
英文描述： Field Programmable Gate Array (FPGA)
中文描述： 現(xiàn)場(chǎng)可編程門陣列（FPGA）
文件頁數(shù)： 18/36頁
文件大?。?/td> 833K
代理商： A54SX32-3TQ176
54SX Family FPGAs RadTolerant and HiRel
18
v2.0
A54SX16 Timing Characteristics
(Worst-Case Military Conditions, V
CCR
= 4.75V, V
CCA,
V
CCI
= 3.0V, T
J
= 125
°
C)
C-Cell Propagation Delays
1
‘–
1
’
Speed
‘
Std
’
Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
t
PD
Predicted Routing Delays
2
Internal Array Module
0.9
1.0
ns
t
DC
t
FC
t
RD1
t
RD2
t
RD3
t
RD4
t
RD8
t
RD12
t
RD18
t
RD24
FO=1 Routing Delay, Direct Connect
0.1
0.1
ns
FO=1 Routing Delay, Fast Connect
0.6
0.7
ns
FO=1 Routing Delay
0.7
0.8
ns
FO=2 Routing Delay
1.2
1.4
ns
FO=3 Routing Delay
1.7
2.0
ns
FO=4 Routing Delay
2.2
2.6
ns
FO=8 Routing Delay
4.3
5.0
ns
FO=12 Routing Delay
5.6
6.6
ns
FO=18 Routing Delay
9.4
11.0
ns
FO=24 Routing Delay
12.4
14.6
ns
R-Cell Timing
t
RCO
t
CLR
t
SUD
t
HD
t
WASYN
Sequential Clock-to-Q
0.6
0.8
ns
Asynchronous Clear-to-Q
0.6
0.8
ns
Flip-Flop Data Input Set-Up
0.8
0.9
ns
Flip-Flop Data Input Hold
0.0
0.0
ns
Asynchronous Pulse Width
2.4
2.9
ns
I/O Module Input Propagation Delays
t
INYH
t
INYL
Predicted Input Routing Delays
3
Input Data Pad-to-Y HIGH
2.2
2.6
ns
Input Data Pad-to-Y LOW
2.2
2.6
ns
t
IRD1
t
IRD2
t
IRD3
t
IRD4
t
IRD8
t
IRD12
t
IRD18
t
IRD24
Notes:
1.
2.
FO=1 Routing Delay
0.7
0.8
ns
FO=2 Routing Delay
1.2
1.4
ns
FO=3 Routing Delay
1.7
2.0
ns
FO=4 Routing Delay
2.2
2.6
ns
FO=8 Routing Delay
4.3
5.0
ns
FO=12 Routing Delay
5.6
6.6
ns
FO=18 Routing Delay
9.4
11.0
ns
FO=24 Routing Delay
12.4
14.6
ns
For dual-module macros, use t
PD
+ t
RD1
+ t
PDn
, t
RCO
+ t
RD1
+ t
PDn
or t
PD1
+ t
RD1
+ t
SUD
, whichever is appropriate.
Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment.
Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment.
3.
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