Table 2-23 A54SX16A Timing Characteristics (Worst-Case Commercial Conditions V
參數(shù)資料
型號: A54SX32A-1CQ208B
廠商: Microsemi SoC
文件頁數(shù): 53/108頁
文件大?。?/td> 0K
描述: IC FPGA SX 48K GATES 208-CQFP
標準包裝: 1
系列: SX-A
LAB/CLB數(shù): 2880
輸入/輸出數(shù): 174
門數(shù): 48000
電源電壓: 2.25 V ~ 5.25 V
安裝類型: 表面貼裝
封裝/外殼: 208-BFCQFP,帶拉桿
供應(yīng)商設(shè)備封裝: 208-CQFP(75x75)
SX-A Family FPGAs
v5.3
2-29
Table 2-23 A54SX16A Timing Characteristics
(Worst-Case Commercial Conditions VCCA = 2.25 V, VCCI = 3.0 V, TJ = 70°C)
Parameter
Description
–3 Speed*
–2 Speed
–1 Speed
Std. Speed
–F Speed
Units
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Dedicated (Hardwired) Array Clock Networks
tHCKH
Input Low to High
(Pad to R-cell Input)
1.2
1.4
1.6
1.8
2.8
ns
tHCKL
Input High to Low
(Pad to R-cell Input)
1.0
1.1
1.3
1.5
2.2
ns
tHPWH
Minimum Pulse Width High
1.4
1.7
1.9
2.2
3.0
ns
tHPWL
Minimum Pulse Width Low
1.4
1.7
1.9
2.2
3.0
ns
tHCKSW
Maximum Skew
0.3
0.4
0.6
ns
tHP
Minimum Period
2.8
3.4
3.8
4.4
6.0
ns
fHMAX
Maximum Frequency
357
294
263
227
167
MHz
Routed Array Clock Networks
tRCKH
Input Low to High (Light Load)
(Pad to R-cell Input)
1.0
1.2
1.3
1.5
2.1
ns
tRCKL
Input High to Low (Light Load)
(Pad to R-cell Input)
1.1
1.3
1.5
1.7
2.4
ns
tRCKH
Input Low to High (50% Load)
(Pad to R-cell Input)
1.1
1.3
1.4
1.7
2.3
ns
tRCKL
Input High to Low (50% Load)
(Pad to R-cell Input)
1.1
1.3
1.5
1.7
2.4
ns
tRCKH
Input Low to High (100% Load)
(Pad to R-cell Input)
1.3
1.5
1.7
2.0
2.7
ns
tRCKL
Input High to Low (100% Load)
(Pad to R-cell Input)
1.3
1.5
1.7
2.0
2.8
ns
tRPWH
Minimum Pulse Width High
1.4
1.7
1.9
2.2
3.0
ns
tRPWL
Minimum Pulse Width Low
1.4
1.7
1.9
2.2
3.0
ns
tRCKSW
Maximum Skew (Light Load)
0.8
0.9
1.0
1.2
1.7
ns
tRCKSW
Maximum Skew (50% Load)
0.8
0.9
1.0
1.2
1.7
ns
tRCKSW
Maximum Skew (100% Load)
1.0
1.1
1.3
1.5
2.1
ns
Note: *All –3 speed grades have been discontinued.
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