參數(shù)資料
型號： A54SX32A-1CQ256C
元件分類： FPGA
英文描述： FPGA, 2880 CLBS, 32000 GATES, 241 MHz, CQFP256
封裝： CERAMIC, QFP-256
文件頁數(shù)： 2/40頁
文件大小： 738K
代理商： A54SX32A-1CQ256C
10
Bou ndar y S can T e s ti ng (BS T )
All SX-A devices are IEEE 1149.1 compliant. SX-A devices
offer superior diagnostic and testing capabilities by
providing Boundary Scan Testing (BST) and probing
capabilities. These functions are controlled through the
special test pins in conjunction with the program fuse. The
functionality of each pin is described in Table 2.
In the dedicated test mode, TCK, TDI, and TDO are
dedicated pins and cannot be used as regular I/Os. In
flexible mode, TMS should be set HIGH through a pull-up
resistor of 10k. TMS can be pulled LOW to initiate the test
sequence.
The program fuse determines whether the device is in
dedicated or flexible mode. The default (fuse not blown) is
flexible mode.
S X - A P rob e C i r cui t Co nt ro l P i ns
The Silicon Explorer II tool uses the boundary scan ports
(TDI, TCK, TMS, and TDO) to select the desired nets for
verification. The selected internal nets are assigned to the
PRA/PRB pins for observation. Figure 7 illustrates the
interconnection between Silicon Explorer II and the FPGA
to perform in-circuit verification. The TRST pin is equipped
with an internal pull-up resistor. To remove the boundary
scan state machine from the reset state during probing, it is
recommended that TRST be left floating.
D e s i gn Con s i der at i o n s
The TDI, TCK, TDO, PRA, and PRB pins should not be used
as input or bidirectional ports. Because these pins are active
during probing, critical signals input through these pins are
not available while probing. In addition, the Security Fuse
should not be programmed because doing so disables the
Probe Circuitry.
Table 2 Boundary Scan Pin Functionality
Program Fuse Blown
(Dedicated Test Mode)
Program Fuse Not Blown
(Flexible Mode)
TCK, TDI, TDO are
dedicated BST pins
TCK, TDI, TDO are flexible
and may be used as I/Os
No need for pull-up resistor
for TMS
Use a pull-up resistor of
10k on TMS
Figure 7 Probe Setup
Silicon Explorer II
TDI
TCK
TDO
TMS
PRA
PRB
Serial Connection
18
Channels
SX-A FPGA
相關(guān)PDF資料
PDF描述
A54SX32A-1CQG208C FPGA, 2880 CLBS, 32000 GATES, 241 MHz, CQFP208
A54SX32A-1CQG256C FPGA, 2880 CLBS, 32000 GATES, 241 MHz, CQFP256
A54SX32A-CQ208C FPGA, 2880 CLBS, 32000 GATES, 206 MHz, CQFP208
A54SX32A-CQ256C FPGA, 2880 CLBS, 32000 GATES, 206 MHz, CQFP256
A54SX32A-CQG208C FPGA, 2880 CLBS, 32000 GATES, 206 MHz, CQFP208
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A54SX32A-1CQ256M 制造商:Microsemi Corporation 功能描述:FPGA SX-A 32K GATES 1800 CELLS 278MHZ 0.25UM/0.22UM 2.5V 256 - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA 228 I/O 256CQFP
A54SX32A-1CQ84 功能描述:IC FPGA SX 48K GATES 84-CQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:SX-A 標準包裝:1 系列:ProASICPLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計:129024 輸入/輸出數(shù):248 門數(shù):600000 電源電壓:2.3 V ~ 2.7 V 安裝類型:表面貼裝 工作溫度:- 封裝/外殼:352-BFCQFP，帶拉桿 供應(yīng)商設(shè)備封裝:352-CQFP（75x75）
A54SX32A-1CQ84B 功能描述:IC FPGA SX 48K GATES 84-CQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:SX-A 標準包裝:1 系列:ProASICPLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計:129024 輸入/輸出數(shù):248 門數(shù):600000 電源電壓:2.3 V ~ 2.7 V 安裝類型:表面貼裝 工作溫度:- 封裝/外殼:352-BFCQFP，帶拉桿 供應(yīng)商設(shè)備封裝:352-CQFP（75x75）
A54SX32A-1CQ84M 制造商:Microsemi Corporation 功能描述:FPGA SX-A 32K GATES 1800 CELLS 278MHZ 0.25UM/0.22UM 2.5V 84C - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA 69 I/O 84CQFP 制造商:Microsemi Corporation 功能描述:IC FPGA 48K GATES 84CQFP
A54SX32A-1FG144 功能描述:IC FPGA SX 48K GATES 144-FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:SX-A 標準包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計:- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27）
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