參數(shù)資料
型號(hào)： A54SX32A-1CQ256C
元件分類： FPGA
英文描述： FPGA, 2880 CLBS, 32000 GATES, 241 MHz, CQFP256
封裝： CERAMIC, QFP-256
文件頁(yè)數(shù)： 8/40頁(yè)
文件大?。?/td> 738K
代理商： A54SX32A-1CQ256C
16
AC Speci ficati ons (3. 3V PCI Operatio n)
Symbol
Parameter
Condition
Min.
Max.
Units
IOH(AC)
Switching Current High
0 < VOUT ≤ 0.3VCCI
1
–12VCCI
mA
0.3VCCI ≤ VOUT < 0.9VCCI
1
(–17.1 + (VCCI – VOUT))
mA
0.7VCCI < VOUT < VCCI
1, 2
(Test Point)
VOUT = 0.7VCC
2
–32VCCI
mA
IOL(AC)
Switching Current Low
VCCI > VOUT ≥ 0.6VCCI
1
16VCCI
mA
0.6VCCI > VOUT > 0.1VCCI
1
(26.7VOUT)mA
0.18VCCI > VOUT > 0
1, 2
(Test Point)
VOUT = 0.18VCC
2
38VCCI
mA
ICL
Low Clamp Current
–3 < VIN ≤ –1
–25 + (VIN + 1)/0.015
mA
ICH
High Clamp Current
VCCI + 4 > VIN ≥ VCCI + 1
25 + (VIN – VCCI – 1)/0.015
mA
slewR
Output Rise Slew Rate
0.2VCCI to 0.6VCCI load
3
14
V/ns
slewF
Output Fall Slew Rate
0.6VCCI to 0.2VCCI load
3
14
V/ns
Notes:
1.
Refer to the V/I curves in Figure 9 on page 17. Switching current characteristics for REQ# and GNT# are permitted to be one half of that
specified here; i.e., half size output drivers may be used on these signals. This specification does not apply to CLK and RST#, which are
system outputs. “Switching Current High” specifications are not relevant to SERR#, INTA#, INTB#, INTC#, and INTD, which are open drain
outputs.
2.
Maximum current requirements must be met as drivers pull beyond the last step voltage. Equations defining these maximums (C and D)
are provided with the respective diagrams in Figure 9 on page 17. The equation defined maxima should be met by design. In order to
facilitate component testing, a maximum current test point is defined for each side of the output driver.
3.
This parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the instantaneous rate at any point
within the transition range. The specified load (diagram below) is optional; i.e., the designer may elect to meet this parameter with an
unloaded output per the latest revision of the PCI Local Bus Specification. However, adherence to both maximum and minimum
parameters is required (the maximum is no longer simply a guideline). Rise slew rate does not apply to open drain outputs.
output
buffer
1/2 in. max.
VCC
1k
10 pF
1k
pin
相關(guān)PDF資料
PDF描述
A54SX32A-1CQG208C FPGA, 2880 CLBS, 32000 GATES, 241 MHz, CQFP208
A54SX32A-1CQG256C FPGA, 2880 CLBS, 32000 GATES, 241 MHz, CQFP256
A54SX32A-CQ208C FPGA, 2880 CLBS, 32000 GATES, 206 MHz, CQFP208
A54SX32A-CQ256C FPGA, 2880 CLBS, 32000 GATES, 206 MHz, CQFP256
A54SX32A-CQG208C FPGA, 2880 CLBS, 32000 GATES, 206 MHz, CQFP208
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A54SX32A-1CQ256M 制造商:Microsemi Corporation 功能描述:FPGA SX-A 32K GATES 1800 CELLS 278MHZ 0.25UM/0.22UM 2.5V 256 - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA 228 I/O 256CQFP
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A54SX32A-1CQ84B 功能描述:IC FPGA SX 48K GATES 84-CQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:SX-A 標(biāo)準(zhǔn)包裝:1 系列:ProASICPLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):129024 輸入/輸出數(shù):248 門數(shù):600000 電源電壓:2.3 V ~ 2.7 V 安裝類型:表面貼裝 工作溫度:- 封裝/外殼:352-BFCQFP，帶拉桿 供應(yīng)商設(shè)備封裝:352-CQFP（75x75）
A54SX32A-1CQ84M 制造商:Microsemi Corporation 功能描述:FPGA SX-A 32K GATES 1800 CELLS 278MHZ 0.25UM/0.22UM 2.5V 84C - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA 69 I/O 84CQFP 制造商:Microsemi Corporation 功能描述:IC FPGA 48K GATES 84CQFP
A54SX32A-1FG144 功能描述:IC FPGA SX 48K GATES 144-FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:SX-A 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計(jì):- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27）
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