參數(shù)資料
型號(hào)： A54SX32A-1CQG208C
元件分類(lèi)： FPGA
英文描述： FPGA, 2880 CLBS, 32000 GATES, 241 MHz, CQFP208
封裝： CERAMIC, QFP-208
文件頁(yè)數(shù)： 37/40頁(yè)
文件大?。?/td> 738K
代理商： A54SX32A-1CQG208C
6
Logi c Modul e Des i gn
The
SX-A
family
architecture
is
described
as
a
“sea-of-modules” architecture because the entire floor of
the device is covered with a grid of logic modules with
virtually no chip area lost to interconnect elements or
routing. Actel’s SX-A family provides two types of logic
modules, the register cell (R-cell) and the combinatorial
cell (C-cell).
The R-cell contains a flip-flop featuring asynchronous clear,
asynchronous preset, and clock enable (using the S0 and S1
lines) control signals (Figure 2). The R-cell registers feature
programmable clock polarity selectable on a register by
register basis. This provides additional flexibility while
allowing mapping of synthesized functions into the SX-A
FPGA. The clock source for the R-cell can be chosen from
either the hardwired clock or the routed clock.
The C-cell implements a range of combinatorial functions
up to 5 inputs (Figure 3 on page 7). Inclusion of the DB
input and its associated inverter function dramatically
increases the number of combinatorial functions that can be
implemented in a single module from 800 options in
previous architectures to more than 4,000 in the SX-A
architecture. An example of the improved flexibility enabled
by the inversion capability is the ability to integrate a
3-input exclusive-OR function into a single C-cell. This
facilitates construction of 9-bit parity-tree functions with
2 ns propagation delays. At the same time, the C-cell
structure is extremely synthesis friendly, simplifying the
overall design and reducing synthesis time.
Chi p Ar chi te c tu re
The SX-A family’s chip architecture provides a unique
approach to module organization and chip routing that
delivers the best register/logic mix for a wide variety of new
and emerging applications.
Mo dul e Or gan i z at i o n
Actel has arranged all C-cell and R-cell logic modules into
horizontal banks called Clusters. There are two types of
Clusters: Type 1 contains two C-cells and one R-cell, while
Type 2 contains one C-cell and two R-cells.
To increase design efficiency and device performance, Actel
has further organized these modules into SuperClusters
(Figure 4 on page 7). SuperCluster 1 is a two-wide grouping
of Type 1 clusters. SuperCluster 2 is a two-wide group
containing one Type 1 cluster and one Type 2 cluster. SX-A
devices feature more SuperCluster 1 modules than
SuperCluster 2 modules because designers typically require
significantly more combinatorial logic than flip-flops.
R out i n g R e s o urc e s
Clusters and SuperClusters can be connected through the
use of two innovative local routing resources called
FastConnect and DirectConnect, which enable extremely
fast and predictable interconnection of modules within
Clusters and SuperClusters (Figure 5 and Figure 6 on
page 8). This routing architecture also dramatically reduces
the number of antifuses required to complete a circuit,
ensuring the highest possible performance.
DirectConnect is a horizontal routing resource that provides
connections from a C-cell to its neighboring R-cell in a given
SuperCluster. DirectConnect uses a hardwired signal path
requiring no programmable interconnection to achieve its
fast signal propagation time of less than 0.1 ns.
Figure 2 R-Cell
Direct
Connect
Input
CLKA,
CLKB,
Internal Logic
HCLK
CKS
CKP
CLRB
PSETB
Y
DQ
Routed
Data Input
S0
S1
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A54SX32A-CQG208C FPGA, 2880 CLBS, 32000 GATES, 206 MHz, CQFP208
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相關(guān)代理商/技術(shù)參數(shù)
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