參數(shù)資料
型號(hào): A54SX32A-CQ256C
元件分類: FPGA
英文描述: FPGA, 2880 CLBS, 32000 GATES, 206 MHz, CQFP256
封裝: CERAMIC, QFP-256
文件頁(yè)數(shù): 18/40頁(yè)
文件大?。?/td> 738K
代理商: A54SX32A-CQ256C
25
Hi R e l S X -A F a m i l y F P G A s
A5 4S X32 A Ti m i ng Ch ar ac te r i s t i c s (Continued)
(W or s t - C as e M i l i t a r y Cond i t i o n s V CCA = 2 .3V , VCCI = 4.75 V, TJ = 1 25°C)
‘–1’ Speed
‘Std’ Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
5.0V PCI Output Module Timing1
tDLH
Data-to-Pad LOW to HIGH
4.7
5.0
ns
tDHL
Data-to-Pad HIGH to LOW
5.2
6.1
ns
tENZL
Enable-to-Pad, Z to L
2.0
2.3
ns
tENZH
Enable-to-Pad, Z to H
2.2
2.6
ns
tENLZ
Enable-to-Pad, L to Z
4.1
4.8
ns
tENHZ
Enable-to-Pad, H to Z
5.1
6.0
ns
dTLH
Delta LOW to HIGH
0.02
0.04
ns/pF
dTHL
Delta HIGH to LOW
0.05
ns/pF
5.0V TTL Output Module Timing2
tDLH
Data-to-Pad LOW to HIGH
3.8
4.5
ns
tDHL
Data-to-Pad HIGH to LOW
4.8
5.6
ns
tENZL
Enable-to-Pad, Z to L
3.9
4.6
ns
tENZH
Enable-to-Pad, Z to H
3.5
4.2
ns
tENLZ
Enable-to-Pad, L to Z
5.1
6.0
ns
tENHZ
Enable-to-Pad, H to Z
6.4
7.3
ns
dTLH
Delta LOW to HIGH
0.02
0.04
ns/pF
dTHL
Delta HIGH to LOW
0.05
ns/pF
Note:
1.
Delays based on 50 pF loading.
2.
Delays based on 35 pF loading.
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