參數(shù)資料
型號(hào)： A54SX32A-CQ256C
元件分類(lèi)： FPGA
英文描述： FPGA, 2880 CLBS, 32000 GATES, 206 MHz, CQFP256
封裝： CERAMIC, QFP-256
文件頁(yè)數(shù)： 5/40頁(yè)
文件大小： 738K
代理商： A54SX32A-CQ256C
13
Hi R e l S X -A F a m i l y F P G A s
AC S pec i f i cat i o n s (5. 0 V P C I Op era ti on)
Symbol
Parameter
Condition
Min.
Max.
Units
IOH(AC)
Switching Current High
0 < VOUT ≤ 1.4
1
–44
mA
1.4
≤ VOUT < 2.4 1, 2
(–44 + (VOUT – 1.4)/0.024)
mA
3.1 < VOUT < VCCI
1, 3
(Test Point)
VOUT = 3.1
3
–142
mA
IOL(AC)
Switching Current Low
VOUT ≥ 2.2
1
95
mA
2.2 > VOUT > 0.55
1
(VOUT/0.023)
mA
0.71 > VOUT > 0
1, 3
(Test Point)
VOUT = 0.71
3
206
mA
ICL
Low Clamp Current
–5 < VIN ≤ –1
–25 + (VIN + 1)/0.015
mA
slewR
Output Rise Slew Rate
0.4V to 2.4V load 4
15
V/ns
slewF
Output Fall Slew Rate
2.4V to 0.4V load 4
15
V/ns
Notes:
1.
Refer to the V/I curves in Figure 8 on page 14. Switching current characteristics for REQ# and GNT# are permitted to be one half of that
specified here; i.e., half size output drivers may be used on these signals. This specification does not apply to CLK and RST#, which are
system outputs. “Switching Current High” specifications are not relevant to SERR#, INTA#, INTB#, INTC#, and INTD#, which are open
drain outputs.
2.
Note that this segment of the minimum current curve is drawn from the AC drive point directly to the DC drive point rather than toward
the voltage rail (as is done in the pull-down curve). This difference is intended to allow for an optional N-channel pull-up.
3.
Maximum current requirements must be met as drivers pull beyond the last step voltage. Equations defining these maximums (A and B)
are provided with the respective diagrams in Figure 8 on page 14. The equation defined maxima should be met by design. In order to
facilitate component testing, a maximum current test point is defined for each side of the output driver.
4.
This parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the instantaneous rate at any point
within the transition range. The specified load (diagram below) is optional; i.e., the designer may elect to meet this parameter with an
unloaded output per revision 2.0 of the PCI Local Bus Specification. However, adherence to both maximum and minimum parameters is
now required (the maximum is no longer simply a guideline). Since adherence to the maximum slew rate was not required prior to
revision 2.1 of the specification, there may be components in the market for some time that have faster edge rates; therefore, motherboard
designers must bear in mind that rise and fall times faster than this specification could occur and should ensure that signal integrity
modeling accounts for this. Rise slew rate does not apply to open drain outputs.
output
buffer
1/2 in. max.
VCC
1k
10 pF
1k
pin
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