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參數(shù)資料
| 型號： | A80960JA-33 |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | EMBEDDED 32-BIT MICROPROCESSOR |
| 中文描述： | 32-BIT, 33 MHz, RISC PROCESSOR, CPGA132 |
| 封裝： | PGA-132 |
| 文件頁數(shù)： | 47/78頁 |
| 文件大小： | 835K |
| 代理商： | A80960JA-33 |
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Advance Information Datasheet
47
80960JA/JF/JD/JT 3.3 V Microprocessor
4.7.1
AC Test Conditions and Derating Curves
The AC Specifications in
Section 4.7, “AC Specifications” are tested with the 50 pF load indicated
in Figure 10. Figure 11 shows how timings and output rise and fall times vary with load
capacitance.
Table 24.
Note Definitions for Table 23, 80960Jx AC Characteristics (pg. 44)
NOTES:
1. Not tested.
2. To ensure a 1:1 relationship between the amplitude of the input jitter and the internal clock, the jitter
frequency spectrum should not have any power peaking between 500 KHz and 1/3 of the CLKIN
frequency.
3. Inactive ALE/ALE refers to the falling edge of ALE and the rising edge of ALE. For inactive ALE/ALE
timings, refer to Relative Output Timings in this table.
4. A float condition occurs when the output current becomes less than I
OL
. Float delay is not tested, but is
designed to be no longer than the valid delay.
5. AD31:0 are synchronous inputs. Setup and hold times must be met for proper processor operation. NMI
and XINT7:0 may be synchronous or asynchronous. Meeting setup and hold time guarantees recognition
at a particular clock edge. For asynchronous operation, NMI and XINT7:0 must be asserted for a
minimum of two CLKIN periods to guarantee recognition.
6. RDYRCV and HOLD are synchronous inputs. Setup and hold times must be met for proper processor
operation.
7. RESET may be synchronous or asynchronous. Meeting setup and hold time guarantees recognition at a
particular clock edge.
8. ONCE and STEST must be stable at the rising edge of RESET for proper operation.
9. Guaranteed by design. May not be 100% tested.
10.Relative to falling edge of TCK.
11.Worst-case T
condition occurs on I/O pins when pins transition from a floating high input to driving a
low output state. The Address/Data Bus pins encounter this condition between the last access of a read,
and the address cycle of a following write. 5 V signals take 3 ns longer to discharge than 3.3 V signals at
50 pF loads.
Figure 10.
AC Test Load
Output Pin
C
L
= 50 pF for all signals
C
L
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| A80960JD | 3.3 V EMBEDDED 32-BIT MICROPROCESSOR |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A80960JA3V25 | 功能描述:IC MPU I960JA 3V 25MHZ 132-PGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:- 標(biāo)準(zhǔn)包裝:60 系列:SCC 處理器類型:Z380 特點:全靜電 Z380 CPU 速度:20MHz 電壓:5V 安裝類型:表面貼裝 封裝/外殼:144-LQFP 供應(yīng)商設(shè)備封裝:144-LQFP 包裝:托盤 |
| A80960JA3V33 | 功能描述:IC MPU I960JA 3V 33MHZ 132-PGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:- 標(biāo)準(zhǔn)包裝:40 系列:MPC83xx 處理器類型:32-位 MPC83xx PowerQUICC II Pro 特點:- 速度:267MHz 電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 封裝/外殼:516-BBGA 裸露焊盤 供應(yīng)商設(shè)備封裝:516-PBGAPGE（27x27） 包裝:托盤 |
| A80960JD | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:3.3 V EMBEDDED 32-BIT MICROPROCESSOR |
| A80960JD-33 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:EMBEDDED 32-BIT MICROPROCESSOR |
| A80960JD3V33 | 功能描述:IC MPU I960JD 3.3V 33MHZ 132-PGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:- 標(biāo)準(zhǔn)包裝:40 系列:MPC83xx 處理器類型:32-位 MPC83xx PowerQUICC II Pro 特點:- 速度:267MHz 電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 封裝/外殼:516-BBGA 裸露焊盤 供應(yīng)商設(shè)備封裝:516-PBGAPGE（27x27） 包裝:托盤 |
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