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5
V
2
=
Q
C1
+
Q
CM
C
1
+
C
M
=
1E
–6
100E
–9
+
50E
–12
=
9.99550V
V
1
= 10V
V = V
1
– V
2
= 4.5mV Error Voltage
As shown in the “normal” circuit in Figure 10, the influence
of C
M
, the multiplexer output capacitance, is easy to see.
Example:
In channel 1, C
M
was charged to 0V. After the switching, C
M
is switched parallel to 100nF (C
1
), which is charged to 10V.
The charge constant of 2k
and 50pF is only 100ns. In
contrast, the recharge time constant from the source to C
1
is
1ms, thus significantly longer. Using simplification, the
charge of C
M
is switched parallel to the 100nF capacitor.
Q
C1
= 100nF 10V
Q
CM
= 50pF 0V
Q
C1
= Q
CM
= 100nF 10V + 50pF 0V
FIGURE 9. Current-Limiting Circuit Using a J-FET.
10k
MUX
MPC50X
OPA27
10k
1μF
1μF
10k
10k
10k
2N4117
Using resistors in the source line of the FET circuit allows
an even greater reduction of the current limitation. This
reduction increases the total resistance in the supply line to
the amplifier input. The FETs alone produce about 10k
+
10k
. To go from the typical 60
μ
A to 30
μ
A, about 10k
are necessary in the source line (see Figure 9). Thus, if the
error current was reduced by half, the total resistance would
rise to 40k
and
40k
is an acceptable value for the error
caused by the bias current. Larger values would cause bias
current errors to exceed the offset errors.
Example:
Bias Current Drift: PGA204AP
Bias Resistance:
I
OS
/
°
C = 8pA/
°
C 40k
= 0.32
μ
V/
°
C
Since the 0.3
μ
V/
°
C is close to the 0.25
μ
V/
°
C offset drift, the
40k
will not cause a significant error over temperature.
The current limitation circuit described here can also be used
as a protection circuit in front of the inputs. The isolation
voltage strength is that of the FETs used. The current is
limited to such a small value that the internal diodes to the
semiconductor substrate is sufficient to redirect the current.
8pA/
°
C
40k
MUX OUTPUT CAPACITANCE
The ON resistances of analog multiplexers can vary greatly
and due to the protection circuitry, can amount up to 2k
(in
this case, the protection circuitry is ohmic resistors). An-
other varying factor is the channel capacitance and, conse-
quently, the capacitance that influences the output. This
capacitance is switched from one channel to the next, is up
to 100pF per IC, and is, of course, dependent upon the
number of channels and the desired on-resistance. At 2k
and 50pF, the settling time constant is 0.1
μ
s. This constant
is negligible for most applications, but as already discussed,
it overloads most amplifiers.
This charge in the output capacitance also produces a
current pulse to the signal source. If, as described above,
the input is configured with the obligatory low-pass filter,
the transferred charge flows into the filter capacitor, pro-
ducing a charge compensation between the two capacitors
that are now in parallel (see Figure 10). Simply the fact that
an additional 50pF filter capacitor is wired parallel to a
100nF capacitor makes it probable that the former, at 2000
times the latter, will have a significant influence on it. Of
course, this configuration does require a break-before-
make; otherwise, further compensation and error currents
arise. This break-before-make, however, can only be main-
tained within an IC. If several multiplexers are cascaded,
problems can easily arise.
FIGURE 10. Mux Capacitance C
M
.
MPC506A
100nF
C
1
100nF
100nF
10k
100nF
2k
10k
2k
10k
2k
10k
2k
C
50pF
16-Channel MUX
CH1
CH2
CH3
CH4
V
OUT