Table 2 Internally Connected" />
參數(shù)資料
型號(hào)： ACS8944T
廠商： Semtech
文件頁(yè)數(shù)： 19/24頁(yè)
文件大?。?/td> 0K
描述： IC JITTER ATT MULT PLL 48-QFN
標(biāo)準(zhǔn)包裝： 1
類型： 時(shí)鐘/頻率發(fā)生器，多路復(fù)用器
PLL： 是
主要目的： SONET/SDH
輸入： LVPECL
輸出： LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 1:1
差分 - 輸入:輸出： 是/是
頻率 - 最大： 155.52MHz
電源電壓： 3.135 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-VFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 48-QFN（7x7）
包裝： 管件
ADVANCED COMMUNICATIONS
FINAL
DATASHEET
Revision 3/November 2006 Semtech Corp.
Page 4
www.semtech.com
ACS8944 JAM PLL
Table 2 Internally Connected (IC)/ Not Connected (NC) Pins
Pin No.
Symbol
I/O
Type
Description
18,19,
37, 41
IC1, IC2,
IC3, IC4,
-
Internally connected. Connect to ground.
42
IC5
-
Internally connected. Connect to VDD.
4, 5,
6, 7,
8, 9,
10, 11,
12, 20,
21, 30,
31, 32,
33, 44,
45, 47,
48
NC1, NC2,
NC3, NC4,
NC5, NC6,
NC7, NC8,
NC9, NC10,
NC11, NC12
NC13, NC14,
NC15, NC16,
NC17, NC18,
NC19
-
Not connected. Leave to float.
Table 3 Functional Pins
Pin No.
Symbol
I/O
Type
Description
2
OUTN
O
LVPECL
LVPECL differential output at a rate from 19.44 MHz up to 155.52 MHz. Partnered with
pin 3. See pin 3 description for more detail.
3
OUTP
O
LVPECL
LVPECL differential output at a rate from 19.44 MHz up to 155.52 MHz. Partnered with
pin 2. The output frequency selection is preset by externally connecting OP_FSEL pin (pin
46), to one from a set of four output frequency pins CFG_OUT[3:0] (Pins 16, 15, 14 and
13); which, on reset will give a corresponding generated output frequency of 19.44 MHz,
38.88 MHz, 77.76 MHz, or 155.52 MHz.
13
CFG_OUT0
O
LVTTL/LVCMOS Configuration pin used to set input reference frequency for CLK (N and P) and output clock
frequency for OUT (N and P) used in conjunction with pins 14, 15, 16, and 46 as defined in
Tables 4 and 5.
14
CFG_OUT1
O
LVTTL/LVCMOS Configuration pin used to set input reference frequency for CLK (N and P) and output clock
frequency for OUT (N and P) used in conjunction with pins 13, 15, 16 and 46 as defined in
Tables 4 and 5.
15
CFG_OUT2
O
LVTTL/LVCMOS Configuration pin used to set input reference frequency for CLK (N and P) and output clock
frequency for OUT (N and P) used in conjunction with pins 13, 14, 16 and 46 as defined in
Tables 4 and 5.
16
CFG_OUT3
O
LVTTL/LVCMOS Configuration pin used to set input reference frequency for CLK (N and P) and output clock
frequency for OUT (N and P) used in conjunction with pins 13, 14, 15 and 46 as defined in
Tables 4 and 5.
17
LOCKB
O
Analog
Lock detect output. This is a pulse width modulated output current, with each pulse
typically +10
A. The output produces a pulse with a width in proportion to the phase error
seen at the internal phase detector. This pin should be connected via an external parallel
capacitor and resistor to ground. The pin voltage will then give an indication of phase lock:
When low, the device is phase locked; when high the device has frequent large phase
errors and so is not phase locked. The value of the RC components used determines the
time and level of consistency required for lock indication.
22
EXT1
I
LVTTL/LVCMOSD Input frequency configuration pin. See Table 4.
23
EXT2
I
LVTTL/LVCMOSD Input frequency configuration pin. See Table 4.
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