參數(shù)資料
型號(hào): ACS8944T
廠商: Semtech
文件頁數(shù): 21/24頁
文件大小: 0K
描述: IC JITTER ATT MULT PLL 48-QFN
標(biāo)準(zhǔn)包裝: 1
類型: 時(shí)鐘/頻率發(fā)生器,多路復(fù)用器
PLL:
主要目的: SONET/SDH
輸入: LVPECL
輸出: LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 1:1
差分 - 輸入:輸出: 是/是
頻率 - 最大: 155.52MHz
電源電壓: 3.135 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 48-QFN(7x7)
包裝: 管件
ADVANCED COMMUNICATIONS
FINAL
DATASHEET
Revision 3/November 2006 Semtech Corp.
Page 6
www.semtech.com
ACS8944 JAM PLL
Voltage Controlled Oscillator
The internal VCO operates at 2.48832 GHz and is
internally divided down to the selected rate giving a
precise 50/50 balanced mark/space ratio for the output.
Jitter Filtering
Input jitter is attenuated by the PLL with the frequency cut-
off point (Fc) at which jitter is either tracked or attenuated
being defined by the -3 dB point, i.e. the position of the
first pole of the PLL loop filter. The bandwidth (frequency
at which the first pole occurs) is defined by the component
value selected for the filter from Table 6.
For 19.44 MHz input, using a loop filter bandwidth of
2kHz gives:
High input jitter attenuation and roll off:
- 20 dB/decade from first loop filter pole, (Fc)
- 40 dB/decade from 2nd pole (typically 10 x Fc)
Jitter peaking is less than 1 dB (dependent on the
loop filter components)
Typical final output jitter, e.g. 2.8 ps rms measured
over the integration range of 12 kHz-20 MHz offset
from carrier.
Jitter Filtering: Partnering with Semtech
Line Card Protection Part
One “Real World” application for the ACS8944 is to use it
to dejitter the clock output from a Semtech ACS8525
LC/P device. In this case it is recommended to set the
ACS8944 PLL to a bandwidth of around 2 kHz to provide
a low jitter total solution. The test results detailed in the
electrical specifications section show the “Real World”
performance of this combination of parts to be a superior
solution when compared with those traditionally using
simple discrete PLLs, and has the following advantages:
Low overall bandwidth, 18 Hz for example—dictated
by the ACS8525.
High input jitter attenuation and roll-off:
First, second and third order roll-off points:
- 20 dB/decade 18 Hz to 750 Hz,
- 40 dB/decade 750 Hz to 200 kHz and
- 60 dB/decade for >200 kHz.
Typical final output jitter, e.g. 2.9 ps rms (measured
over the integration range 12 kHz-20 MHz)—dictated
by the ACS8944.
High frequency stability when all input clocks fail;
holdover frequency control to Stratum 3—dictated by
the ACS8525.
Input Jitter Tolerance
Jitter tolerance is defined as the maximum amplitude of
sinusoidal jitter that can exist on the input reference clock
above which the device fails to maintain lock. For the
ACS8944 device, the jitter tolerance is shown in Figure 3.
Figure 3 Jitter Tolerance; ACS8944 Standalone
Jitter Transfer
Jitter transfer is a ratio of input jitter present on the
reference clock to the filtered jitter present on the output
clock. Standalone, the Jitter Transfer Characteristic is
defined solely by the loop filter bandwidth and is shown in
Table 5 Output Frequency Selection
For Output Frequency of
Connect OP_FSEL to
19.44 MHz
CFG_OUT3
38.88 MHZ
CFG_OUT2
77.76 MHz
CFG_OUT1
155.52 MHz
CFG_OUT0
Input Jitter Tolerance With 2kHz PLL Bandwidth
0.01
0.1
1
10
100
1000
10
100
1000
10000
100000
1000000
Jitter Frequency Offset from Carrier (Hz)
In
p
u
t
J
it
te
rA
m
p
lit
ud
e
p
-p
(
U
I)
ACS8946 Jitter
Tolerance
OC_12
Tolerance Mask
OC_48
Tolerance Mask
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