AD13280
Rev. C | Page 4 of 28
SPECIFICATIONS
AVCC = +5 V, AVEE = 5 V, DVCC = +3.3 V; applies to each ADC with front-end amplifier, unless otherwise noted.
Table 1.
AD13280AZ
Parameter
Temperature
Test Level
Min
Typ
Max
Unit
RESOLUTION
12
Bits
No Missing Codes
Full
IV
Guaranteed
Offset Error
25°C
I
2.2
±1.0
+2.2
% FS
Full
VI
2.2
±1.0
+2.2
% FS
Offset Error Channel Match
Full
VI
1.0
±0.1
+1.0
%
25°C
I
3
1.0
+1
% FS
Full
VI
5.0
±2.0
+5.0
% FS
Gain Error Channel Match
25°C
I
1.5
±0.5
+1.5
%
Max
VI
3.0
±1.0
+3.0
%
Min
VI
5
±1.0
+5
%
SINGLE-ENDED ANALOG INPUT
Input Voltage Range
AMP-IN-X-1
Full
V
±0.5
V
AMP-IN-X-2
Full
V
±1.0
V
Input Resistance
AMP-IN-X-1
Full
IV
99
100
101
Ω
AMP-IN-X-2
Full
IV
198
200
202
Ω
Capacitance
25°C
V
4.0
7.0
pF
Full
V
143
MHz
DIFFERENTIAL ANALOG INPUT
Analog Signal Input Range
A+IN to A–IN and B+IN to
BIN4Full
V
±1
V
Input Impedance
25°C
V
618
Ω
Analog Input Bandwidth
Full
V
50
MHz
ENCODE INPUT (ENCODE, ENCODE
)1Differential Input Voltage
Full
IV
0.4
V p-p
Differential Input Resistance
25°C
V
10
kΩ
Differential Input Capacitance
25°C
V
2.5
pF
SWITCHING PERFORMANCE
Full
VI
80
MSPS
Full
IV
30
MSPS
Aperture Delay (tA)
25°C
V
0.9
ns
Aperture Delay Matching
25°C
IV
250
500
ps
Aperture Uncertainty (Jitter)
25°C
V
0.3
ps rms
ENCODE Pulse Width High at Max Conversion Rate
25°C
IV
4.75
6.25
8
ns
ENCODE Pulse Width Low at Max Conversion Rate
25°C
IV
4.75
6.25
8
ns
Output Delay (tOD)
Full
V
5
ns
Encode, Rising to Data Ready, Rising Delay
Full
V
8.5
ns
Analog Input @ 10 MHz
25°C
I
66.5
70
dBFS
Min
II
64.5
dBFS
Max
II
66.3
dBFS
Analog Input @ 21 MHz
25°C
I
66.5
70
dBFS
Min
II
64
dBFS
Max
II
66.3
dBFS