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參數(shù)資料
| 型號： | AD13280/PCB |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 7/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | KIT EVAL PCB FOR AD13280 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 2 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 80M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 輸入范圍： | ±1 V |
| 在以下條件下的電源（標(biāo)準(zhǔn)）： | 3.7W @ 80MSPS |
| 工作溫度： | -25°C ~ 85°C |
| 已用 IC / 零件： | AD13280 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | AD13280AZ-ND - IC ADC 12BIT 68CLCC AD13280AF-ND - IC ADC 12BIT 68CLCC |
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AD13280
Rev. C | Page 15 of 28
APPLICATIONS INFORMATION
ENCODING THE AD13280
The AD13280 encode signal must be a high quality, extremely
low phase noise source to prevent degradation of performance.
Maintaining 12-bit accuracy at 80 MSPS places a premium on
encode clock phase noise. SNR performance can easily degrade
3 dB to 4 dB with 37 MHz input signals when using a high jitter
clock source. See Analog Devices Application Note AN-501,
Aperture Uncertainty and ADC System Performance, for com-
plete details. For optimum performance, the AD13280 must be
clocked differentially. The encode signal is usually ac-coupled
into the ENCODE and ENCODE pins via a transformer or
capacitors. These pins are biased internally and require no
additional bias.
Figure 17 shows one preferred method for clocking the AD13280.
The clock source (low jitter) is converted from single-ended to
differential using an RF transformer. The back-to-back Schottky
diodes across the transformer secondary limit clock excursions
into the AD13280 to approximately 0.8 V p-p differential. This
helps prevent the large voltage swings of the clock from feeding
through to the other portions of the AD13280 and limits the
noise presented to the ENCODE inputs. A crystal clock
oscillator can also be used to drive the RF transformer if an
appropriate limited resistor (typically 100 Ω) is placed in series
with the primary.
T1-4T
100
0.1F
ENCODE
AD13280
HSMS2812
DIODES
CLOCK
SOURCE
023
86
-01
7
Figure 17. Crystal Clock Oscillator—Differential Encode
If a low jitter ECL/PECL clock is available, another option is to
ac-couple a differential ECL/PECL signal to the encode input
pins as shown below. A device that offers excellent jitter per-
formance is the MC100LVEL16 (or within the same family)
from Motorola.
ENCODE
AD13280
0.1F
ECL/PECL
VT
0.1F
02
38
6-
01
8
Figure 18. Differential ECL for Encode
JITTER CONSIDERATION
The signal-to-noise ratio for any ADC can be predicted. When
normalized to ADC codes, Equation 1 accurately predicts the
SNR based on three terms. These are jitter, average DNL error,
and thermal noise. Each of these terms contributes to the noise
within the converter.
()
2
/
1
2
1
log
20
+
×
+
+
×
=
N
rms
NOISE
rms
J
ANALOG
N
V
t
f
SNR
π
ε
(1)
where:
fANALOG is the analog input frequency.
tJ rms is the rms jitter of the encode (rms sum of encode source
and internal encode circuitry).
ε is the average DNL of the ADC (typically 0.50 LSB).
N is the number of bits in the ADC.
VNOISE rms is the analog input of the ADC (typically 5 LSB).
For a 12-bit analog-to-digital converter like the AD13280,
aperture jitter can greatly affect the SNR performance as the
analog frequency is increased. The chart below shows a family
of curves that demonstrates the expected SNR performance of
the AD13280 as jitter increases. The chart is derived from
Equation 1.
For a complete discussion of aperture jitter, consult Analog
Devices Application Note AN-501, Aperture Uncertainty and
ADC System Performance.
CLOCK JITTER (ps)
0.
0
0.
2
0.
6
1.
0
1.
4
1.
8
2.
2
2.
6
3.
0
3.
4
0.
4
0.
8
1.
2
1.
6
2.
0
2.
4
2.
8
3.
2
3.
6
SN
R
(–
d
B
F
S
)
60
61
62
63
64
65
66
67
68
69
70
71
59
58
3.
8
4.
0
AIN = 5MHz
AIN = 10MHz
AIN = 20MHz
AIN = 37MHz
02
38
6-
01
9
Figure 19. SNR vs. Jitter
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| AD132IV | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRANSISTOR | BJT | PNP | 60V V(BR)CEO | 3A I(C) | TO-3 |
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