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參數(shù)資料
| 型號： | AD1836ACSZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 4/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CODEC 4ADC/6DAC 24 BIT 52MQFP |
| 標準包裝： | 1 |
| 類型： | 通用 |
| 數(shù)據(jù)接口： | 串行 |
| 分辨率（位）： | 24 b |
| ADC / DAC 數(shù)量： | 4 / 6 |
| 三角積分調(diào)變： | 是 |
| S/N 比，標準 ADC / DAC (db)： | 105 / 108 |
| 動態(tài)范圍，標準 ADC / DAC (db)： | 105 / 108 |
| 電壓 - 電源，模擬： | 4.75 V ~ 5.25 V |
| 電壓 - 電源，數(shù)字： | 4.75 V ~ 5.25 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 52-QFP |
| 供應(yīng)商設(shè)備封裝： | 52-MQFP（10x10） |
| 包裝： | 托盤 |
| 配用： | AD1836AZ-DBRD-ND - BOARD EVAL FOR AD1836A |
AD1836A
Data Sheet
Rev. A | Page 12 of 24
through an FPGA or other large digital chip before being
applied to the AD1836A. In most cases, this will induce clock
jitter due to the fact that the clock signal is sharing common
power and ground connections with other unrelated digital
output signals.
The six DAC channels use a common serial bit clock to clock in
the serial data and a common left-right framing clock. The four
ADC channels output a common serial bit clock and a left-right
framing clock. The clock signals are all synchronous with the
sample rate.
RESET AND POWER-DOWN
Reset will power down the chip and set the control registers to
their default settings. After reset is de-asserted, an initialization
routine will run inside the AD1836A to clear all memories to
zero. This initialization lasts for approximately 4500 MCLKs.
The power-down bit in the DAC Control Register 1 and ADC
Control Register 1 will power down the respective digital
section. The analog circuitry does not power down. All other
register settings are retained.
To avoid possible synchronization problems, if MCLK is 512 fS
or 768 fS, the clock rate should be set in ADC Control Register 3
within the first 3072 MCLK cycles after reset, or DLRCLK and
DBCLK should be withheld until after the internal initialization
completes (see above).
SERIAL CONTROL PORT
The AD1836A has an SPI compatible control port that permits
programming the internal control registers for the ADCs and
DACs and for reading the ADC signal level from the internal
peak detectors. The DAC output levels may be independently
programmed by means of an internal digital attenuator
adjustable in 1024 linear steps.
The SPI control port is a 4-wire serial control port. The format
is similar to the Motorola SPI format except the input data-word
is 16 bits wide. The maximum serial bit clock frequency is 8 MHz
and may be completely asynchronous to the sample rate of the
ADCs and DACs. Figure 3 shows the format of the SPI signal.
All control registers are write-only. They cannot be read back.
The ADC peak registers are read-only. They are reset to zero each
time they are read and are updated at the next sample time.
Due to an anomaly in the SPI interface, when a write to a DAC
control register follows after a read or a write to an ADC
register, it may not be executed properly. Any such write should
be performed twice.
CLATCH
CCLK
CDATA
COUT
D15
D9
D0
D14
D8
D0
Figure 3. Format of SPI Signal
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD1836A-DBRD | 制造商:Analog Devices 功能描述:Evaluation Board For Multi-Channel 96 KHz Codec 制造商:Rochester Electronics LLC 功能描述:EVAL BD FOR MULTI CHANNEL 96KHZ CODEC - Bulk 制造商:Analog Devices 功能描述:EVALUATION BOARD ((NS)) |
| AD1836AS | 制造商:Rochester Electronics LLC 功能描述:ULTI CHANNEL 96KHZ CODEC - Bulk |
| AD1836ASRL | 制造商:Analog Devices 功能描述: |
| AD1836AXS | 制造商:ADI 功能描述: 制造商:Microsemi Corporation 功能描述: |
| AD1836AZ-DBRD | 功能描述:BOARD EVAL FOR AD1836A RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標準包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
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