參數(shù)資料
型號(hào): AD1836AZ-DBRD
廠商: Analog Devices Inc
文件頁數(shù): 8/24頁
文件大?。?/td> 0K
描述: BOARD EVAL FOR AD1836A
標(biāo)準(zhǔn)包裝: 1
主要目的: 音頻編解碼器
嵌入式:
已用 IC / 零件: AD1836A
主要屬性: 3 個(gè)立體聲 DAC -95 dB THD + N,108 dB SNR,2 個(gè)立體聲 ADC -92 dB THD + N,105 dB SNR
次要屬性: 接受 16/18/20/24 位數(shù)據(jù),SPI 接口,支持 48 或 96 kHz 采樣率
已供物品:
產(chǎn)品目錄頁面: 776 (CN2011-ZH PDF)
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AD1836A
Data Sheet
Rev. A | Page 16 of 24
FSTDM
ADC L0
ADC L1
AUX_ADC L0 AUX_ADC L1
ADC R0
INTERNAL
ADC R1
AUX_ADC R0 AUX_ADC R1
DAC L0
DAC L1
DAC L2
AUX_DAC L0
DAC R0
DAC R1
DAC R2
AUX_DAC R0
MSB TDM
1ST
CH
LEFT
RIGHT
I2S
––MSB LEFT
BCLK
TDM
ASDATA1
TDM (OUT)
ASDATA1
DSDATA1
AUX
LRCLK I2S
(FROM AUX ADC NO. 1)
AUX
BCLK I2S
(FROM AUX ADC NO. 1)
AAUXDATA1 (IN)
(FROM AUX ADC NO. 1)
AAUXDATA2 (IN)
(FROM AUX ADC NO. 2)
DAUXDATA (OUT)
(TO AUX DAC)
NOTE
AUX BCLK FREQUENCY IS 64
× FRAME RATE; TDM BCLK FREQUENCY IS 256 × FRAME RATE.
FSTDM FOLLOWS AUX LRCLK BY 3 1/2 ± 1/2 TDM BCLK IN BOTH MASTER AND SLAVE MODES.
TDM
INTERFACE
AUX
I
2
S
INTERFACE
MSB TDM
8TH
CH
32
1ST
CH
MSB TDM
8TH
CH
TDM (IN)
INTERNAL
MSB TDM
INTERNAL
I2S
––MSB LEFT
I2S
––MSB LEFT
I2S
––MSB RIGHT
I2S
––MSB RIGHT
I2S
––MSB RIGHT
Figure 9. AUX Mode Timing (Note that the Clocks Are Not to Scale)
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