REV. 0
–4–
AD1955
SPECIFICATIONS (continued)
GROUP DELAY
Chip Mode
Group Delay Calculation
fS (kHz)
Group Delay
Unit
INT8
Mode
5553/(128
fS)48
903.8
s
INT4
Mode
5601/(64
fS)96
911.6
s
INT2
Mode
5659/(32
fS)
192
921
s
Specifications subject to change without notice.
DIGITAL TIMING (Guaranteed over –40 C to +85 C, AVDD = DVDD = 5.0 V 10%.)
Parameter
Description
Min
Unit
tDMP
MCLK Period (FMCLK = 256
FLRCLK)50
ns
tDML
MCLK LO Pulsewidth (All Modes)
0.4
tDMP
ns
tDMH
MCLK HI Pulsewidth (All Modes)
0.4
tDMP
ns
tDBH
BCLK/EF_BCLK High
20
ns
tDBL
BCLK/EF_BCLK Low
20
ns
tDBP
BCLK/EF_BCLK Period
60
ns
tDLS
LRCLK/EF_WCLK Setup
0
ns
tDLH
LRCLK Hold (DSP Serial Port Mode Only)
15
ns
tDWH
EF_WCLK High
20
ns
tDWL
EF_WCLK Low
20
ns
tDDS
SDATA/EF_LDATA/EF_RDATA Setup
0
ns
tDDH
SDATA/EF_LDATA/EF_RDATA Hold
20
ns
tDPHS
DSD_PHASE Setup
20
ns
tDSDS
DSD_DATA Setup
5
ns
tDSDH
DSD_DATA Hold
5
ns
tDSKP
DSD_SCLK Period
60
ns
tDSKH
DSD_SCLK High
20
ns
tDSKL
DSD_SCLK Low
20
ns
tDMP
CCLK Period
50
ns
tDML
CCLK LO Pulsewidth
15
ns
tDMH
CCLK HI Pulsewidth
10
ns
tCLS
CLATCH Setup
0
ns
tCLH
CLATCH Hold
15
ns
tCDS
CDATA Setup
0
ns
tCDH
CDATA Hold
5
ns
tRSTL
RST LO Pulsewidth
10
ns
Specifications subject to change without notice.