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參數(shù)資料
| 型號： | AD22057N |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 運動控制電子 |
| 英文描述： | RD Series - Econoline Unregulated DC-DC Converters; Input Voltage (Vdc): 12V; Output Voltage (Vdc): 12V; Power: 2W; Low Cost 2W Dual Output Converter; Industry Standard SIP7 and DIP14 Packages; Power Sharing on Outputs; Optional Continuous Short Circuit Protected; 1kVDC & 2kVDC Isolation Options; UL94V-0 Package Material; Efficiency to 86% |
| 中文描述： | INSTRUMENTATION AMPLIFIER, 1000 uV OFFSET-MAX, 0.03 MHz BAND WIDTH, PDIP8 |
| 封裝： | MINI, PLASTIC, DIP-8 |
| 文件頁數(shù)： | 7/8頁 |
| 文件大小： | 192K |
| 代理商： | AD22057N |
AD22057
–7–
REV. A
APPLICAT ION HINT S
Frequency Compensation
As are all closed-loop op amp circuits, the AD22057 is sensitive
to capacitive loading at its output. However, the AD22057 is
sensitive at higher output voltages due to nonlinear effects in
the rail-to-rail design of the buffer amplifier (A2). In this
amplifier the output stage gain increases with increasing output
voltage. T his behavior does not affect dc parameters such as
gain accuracy or linearity; however, it can compromise ac sta-
bility. When operating from a power supply of 5 V or less (and,
therefore, V
OUT
< 5 V), the AD22057 can drive capacitive
loads up to 25 pF with no external components. When operat-
ing at higher supply voltages (which are associated with higher
output voltages) and/or driving larger capacitive loads, an exter-
nal compensation network should be used. Figure 14 shows an
R-C “snubber” circuit loading the output of the AD22057.
T his combination, in conjunction with the internal 20 k
resis-
tance, forms a lag network. T his network attenuates the open-
loop gain of the amplifier at higher frequencies. T he ratio of
R
LAG
to the load seen by the AD22057 determines the high
frequency attenuation seen by the op amp. If R
LAG
is made
1/20th of the total load resistance (
≈
20 k
i
R
L
), then 26 dB of
attenuation is obtained at higher frequencies. T he capacitor
(C
LAG
) is used to control the frequency of the compensation
network. It should be set to form a 5
μ
s time constant with the
resistor (R
LAG
). T able I shows the recommended values of
R
LAG
and C
LAG
for various values of external load resistor R
L
.
T en percent tolerance on these components is acceptable.
Alternatively, the signal may be taken from the midpoint of
R
LAG
–C
LAG
. T his output is particularly useful when driving
CMOS analog-to-digital converters. For more information see
the section Driving Charged Redistributed A/D Converters.
Note that when implementing this network large signal re-
sponse is compromised. T his occurs because there is no active
pull-down and the lag capacitor must discharge through the
internal feedback resistor (20 k
) giving a fairly long-time
constant. For example if C
L AG
= 0.01
μ
F, the large signal
negative slew characteristic is a decaying exponential with a
time constant of
≈
200
μ
s.
T able I. Compensation Components vs. E xternal Load
Resistor
R
L
>100 k
>
50 k
>
20 k
>
10 k
>
5 k
>
2 k
R
LAG
470
390
270
200
100
47
C
LAG
0.01
μ
F
0.01
μ
F
0.047
μ
F
0.047
μ
F
0.1
μ
F
0.22
μ
F
Driving Charge Redistribution A/D Converters
When driving CMOS ADCs, such as those embedded in popu-
lar microcontrollers, the charge injection (
Q) can cause a
significant deflection in the AD22057 output voltage. T hough
generally of short duration, this deflection may persist until
after the sample period of the ADC has expired. It is due to the
relatively high open-loop output impedance of the AD22057.
T he effect can be significantly reduced by including the same
R-C network recommended for improving stability (see Fre-
quency Compensation section). T he large capacitor in the lag
network helps to absorb the additional charge, effectively lower-
ing the high frequency output impedance of the AD22057. For
these applications the output signal should be taken from the
midpoint of the R
LAG
–C
LAG
combination as shown in Figure 15.
Since the perturbations from the analog-to-digital converter are
small, the output of the AD22057 will appear to be a low
impedance. T he transient response will, therefore, have a
time constant governed by the product of the two lag compo-
nents, C
LAG
×
R
LAG
. For the values shown in Figure 15, this
time constant is programmed at approximately 10
μ
s. T here-
fore, if samples are taken at several tens of microseconds or more,
there will be negligible “stacking up” of the charge injections.
10k
V
+V
S
10k
V
LOAD
AD22057
A2
R
LAG
C
LAG
R
L
C
L
Figure 14. Using an R-C Network for Compensation
0.01
m
F
1k
V
10k
V
+V
S
10k
V
AD22057
A2
m
PROCESSOR
A/D
IN
Figure 15. Recommended Circuit for Driving CMOS A/D
Converters
UNDE RST ANDING T HE AD22057
Figure 16 shows the main elements of the AD22057. T he signal
inputs at Pins 1 and 8 are first applied to dual resistive attenua-
tors R1 through R4, whose purpose is to reduce the common-
mode voltage at the input to the preamplifier. T he attenuated
signal is then applied to a feedback amplifier based on the very
low drift op amp, A1. T he differential voltage across the inputs
is accurately amplified in the presence of common-mode volt-
ages of many times the supply voltage. T he overall common-
mode response is minimized by precise laser trimming of R3
and R4, giving the AD22057 a common-mode rejection ratio
(CMRR) of at least 80 dB (10,000:1).
T he common-mode range of A1 extends from slightly below
ground to 1 V below +V
S
(at the minimum temperature of
–40
°
C). Since an attenuation ratio of about 6 is used, the input
common-mode range is –1 V to +24 V using a +5 V supply.
Small filter capacitors C1 and C2 are included to minimize the
effects of spurious RF signals at the inputs, which might cause
dc errors due to the rectification effects at the input to A1. At
high frequencies, even a small imbalance in these components
would seriously degrade the CMRR, so a special high frequency
trim is also carried out during manufacture.
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| AD22100AR | RD Series - Econoline Unregulated DC-DC Converters; Input Voltage (Vdc): 12V; Output Voltage (Vdc): 15V; Power: 2W; Low Cost 2W Dual Output Converter; Industry Standard SIP7 and DIP14 Packages; Power Sharing on Outputs; Optional Continuous Short Circuit Protected; 1kVDC & 2kVDC Isolation Options; UL94V-0 Package Material; Efficiency to 86% |
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