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參數(shù)資料
| 型號： | AD22057N |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 運動控制電子 |
| 英文描述： | RD Series - Econoline Unregulated DC-DC Converters; Input Voltage (Vdc): 12V; Output Voltage (Vdc): 12V; Power: 2W; Low Cost 2W Dual Output Converter; Industry Standard SIP7 and DIP14 Packages; Power Sharing on Outputs; Optional Continuous Short Circuit Protected; 1kVDC & 2kVDC Isolation Options; UL94V-0 Package Material; Efficiency to 86% |
| 中文描述： | INSTRUMENTATION AMPLIFIER, 1000 uV OFFSET-MAX, 0.03 MHz BAND WIDTH, PDIP8 |
| 封裝： | MINI, PLASTIC, DIP-8 |
| 文件頁數(shù)： | 8/8頁 |
| 文件大?。?/td> | 192K |
| 代理商： | AD22057N |
AD22057
–8–
REV. A
P
AD22057
A1
A2
+V
S
R12
100k
V
A2
C1
5pF
R1
200k
V
R18
1k
V
A1
R19 1k
V
C2
5pF
R4
41k
V
R9
10k
V
R7
250
V
R17
95k
V
R15
10k
V
OUT
R16
10k
V
R14
20k
V
R13
20k
V
R5
2.6k
V
R3
41k
V
GND
OFS
R6
250k
V
R8
9k
V
R2
200k
V
R11
2k
V
R10
2k
V
IN+
IN–
Figure 16. Simplified Schematic of AD22057, Including Component Values
OUT LINE DIME NSIONS
Dimensions shown in inches and (mm).
Plastic SOIC Package
(SO-8)
0.1968 (5.00)
0.1890 (4.80)
8
5
4
1
0.2440 (6.20)
0.2284 (5.80)
PIN 1
0.1574 (4.00)
0.1497 (3.80)
0.0688 (1.75)
0.0532 (1.35)
SEATING
PLANE
0.0098 (0.25)
0.0040 (0.10)
0.0192 (0.49)
0.0138 (0.35)
0.0500
(1.27)
BSC
0.0098 (0.25)
0.0075 (0.19)
0.0500 (1.27)
0.0160 (0.41)
8
8
0
8
0.0196 (0.50)
0.0099 (0.25)
3
45
8
Plastic Mini-DIP Package
(N-8)
8
1
4
5
0.430 (10.92)
0.348 (8.84)
0.280 (7.11)
0.240 (6.10)
PIN 1
SEATING
PLANE
0.022 (0.558)
0.014 (0.356)
0.060 (1.52)
0.015 (0.38)
0.210 (5.33)
MAX
0.130
(3.30)
MIN
0.070 (1.77)
0.045 (1.15)
0.100
(2.54)
BSC
0.160 (4.06)
0.115 (2.93)
0.325 (8.25)
0.300 (7.62)
0.015 (0.381)
0.008 (0.204)
0.195 (4.95)
0.115 (2.93)
C
A unique method of feedback around A1, provided by R9 and
R7, sets the closed-loop gain of the preamplifier to
×
10 (from
the input pins). T he feedback network is balanced by the inclu-
sion of R6 and R8. T he small value of R7 results in a more
practical value for R9 (which would have to be 2 M
if the
feedback were taken directly to the inputs of A1). R8 is not
directly connected to ground, but to an optional voltage of one
half that is applied to Pin 7 (OFS). It is trimmed to within close
tolerances through R10 and R11. T his allows the output of A1
to be offset to midscale, typically +V
S
/2, by tying Pins 6 and 7
together. (For an example of the use of this feature, see Figure
12.) T he gain is adjusted by the single resistor R5, which acts
only on the differential signal. More importantly, it also results
in much less feed forward of the common-mode signal to the
output of A1, which, being a single-supply circuit, has no means
of pulling this output down toward ground in those circum-
stances where the common-mode input is very positive while the
net differential signal is small. (T he output of A1 is the collector
of a PNP transistor whose emitter is tied to +V
S
.) R16 is specifi-
cally included to alleviate this problem.
T he output of the preamplifier is connected to Pin 3 via R12, a
100 k
resistor that is trimmed to within
±
3%. T he inclusion of
R12 allows a low-pass filter to be formed, with an accurate time
constant, by placing a capacitor from Pin 3 to ground. By sepa-
rating the connections at Pins 3 and 4, a two-pole Sallen and
K ey filter can be formed (see Low-Pass Filtering section) and
also provides a means for setting the overall gain to values other
than
×
20 (see
Altering the Gain section).
T he output buffer has a gain of
×
2, set by the feedback network
around op amp A2, formed by R15 and R13
i
R14. Note that this
gain is not trimmed to a precise value, but may have a tolerance
of
±
3% (max). Only the overall gain of A1 and A2 is trimmed to
within
±
0.5% by R5. As a consequence, the gain of A1 may be
in error by
±
3% (max) as the trim to R5 absorbs the initial error
in the gain of A2. In most applications Pins 3 and 4 are simply
tied together, but the output buffer can be used independently if
desired. T he offset voltage of A2 is nulled during manufacture.
R17 is included to minimize the offset due to bias currents. It is
recommended, in applications where A2 is used independently
and the source resistance is less than 100 k
, that the necessary
extra resistance should be included.
T he output of A2 is the collector of a PNP transistor whose
emitter is tied to +V
S
. T he bias current out of the inverting
input of this amplifier generates an offset voltage of about +1 mV
in R13
i
R14, which is passed directly to the output via R15. T his
sets the lowest output that can be reached when there is no load
resistor. However, the output can drive a 1 k
load to at least
+4.5 V when +V
S
= +5 V. If operation to much lower minimum
voltages is essential, a load resistor can be added externally.
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