參數(shù)資料
型號： AD2S1210CSTZ
廠商： Analog Devices Inc
文件頁數(shù)： 18/36頁
文件大?。?/td> 0K
描述： IC CONV R/D VAR RES OSC 48-LQFP
標(biāo)準(zhǔn)包裝： 1
類型： R/D 轉(zhuǎn)換器
分辨率（位）： 10，12，14，16 b
數(shù)據(jù)接口： 串行，并聯(lián)
電壓電源： 模擬和數(shù)字
電源電壓： 4.75 V ~ 5.25 V
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-LQFP（7x7）
包裝： 托盤
配用： EVAL-AD2S1210EDZ-ND - BOARD EVAL AD2S1210
AD2S1210
Rev. A | Page 25 of 36
Clearing the Fault Register
The LOT pin and/or the DOS pin of the AD2S1210 are taken
low to indicate that a fault has been detected. The AD2S1210 is
capable of detecting eight separate fault conditions. To determine
which condition triggered the fault indication, the user is required
to enter configuration mode and read the fault register. To reset
the fault indicators, an additional SAMPLE pulse is required.
This ensures that any faults that may occur between the initial
sampling and subsequent reading of the fault register are captured.
Therefore, to read and clear the fault register, the following
sequence of events is required:
1.
A high-to-low transition of the SAMPLE input.
2.
The SAMPLE input should be held low for t16 ns and then
can be returned high.
3.
The AD2S1210 should be put into configuration mode,
that is, A0 and A1 are both set to logic high.
4.
The fault register should be read as described in the
section.
5.
A second high-to-low transition of the SAMPLE input
clears the fault indications on the DOS and/or LOT pins.
6.
Note that in the event of a persistent fault, the fault indica-
tors are reasserted within the specified fault time latency.
Figure 31 shows the timing specifications to follow when
clearing the fault register.
Note that the last valid register address written to the AD2S1210
prior to exiting configuration mode is again valid when reentering
configuration mode. It is therefore recommended that when
initial configuration of the AD2S1210 is complete, the fault address
should be written to the AD2S1210 before leaving configuration
mode. This simplifies the reading and clearing of the fault register
in normal operation because it is now possible to access the
position, velocity, and fault information by toggling the A0 and
A1 pins without requiring additional register addressing.
fCLKIN
t1
t8
t1
t3
t4
t2
t6
t7
t9
t5
t2
CLKIN
A0, A1
CS
WR
DB0 TO DB7
ADDRESS
DATA
NOTES
1.
2. RD SHOULD BE HELD HIGH WHEN WRITING TO THE AD2S1210.
DON’T CARE.
07
46
7-
0
27
Figure 28. Parallel Port Write Timing—Configuration Mode
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