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參數(shù)資料
| 型號(hào)： | AD2S1210DSTZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 26/36頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CONV R/D VAR RES OSC 48LQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | R/D 轉(zhuǎn)換器 |
| 分辨率（位）： | 10，12，14，16 b |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 電壓電源： | 模擬和數(shù)字 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁(yè)面： | 790 (CN2011-ZH PDF) |
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AD2S1210
Rev. A | Page 32 of 36
CIRCUIT DYNAMICS
LOOP RESPONSE MODEL
0
74
67
-03
7
ERROR
(ACCELERATION)
–
θIN
θOUT
VELOCITY
k1 × k2
1 – z–1
1 – bz–1
1 – z–1
c
1 – az–1
c
Sin/Cos LOOKUP
Figure 38. RDC System Response Block Diagram
The RDC is a mixed-signal device that uses two ADCs to digitize
signals from the resolver and a Type II tracking loop to convert
these to digital position and velocity words.
The first gain stage consists of the ADC gain on the sine/cosine
inputs and the gain of the error signal into the first integrator.
The first integrator generates a signal proportional to velocity.
The compensation filter contains a pole and a zero that are used
to provide phase margin and reduce high frequency noise gain.
The second integrator is the same as the first and generates the
position output from the velocity signal. The sin/cos lookup has
unity gain. The values for the k1, k2, a, b, and c parameters are
outlined in Table 28.
The following equations outline the transfer functions of the
individual blocks as shown in Figure 38, which then combine to
form the complete RDC system loop response.
Integrator1 and Integrator2 transfer function
1
)
(
=
z
c
z
I
(10)
Compensation filter transfer function
1
)
(
=
bz
az
z
C
(11)
RDC open-loop transfer function
)
(
)
(
)
(
2
z
C
z
I
k2
k1
z
G
×
=
(12)
RDC closed-loop transfer function
)
(
1
)
(
)
(
z
G
z
G
z
H
+
=
(13)
The closed-loop magnitude and phase responses are that of a
To convert G(z) into the s-plane, an inverse bilinear transforma-
tion is performed by substituting the following equation for z:
s
t
s
t
z
+
=
2
(14)
where t is the sampling period (1/4.096 MHz ≈ 244 ns).
Substitution yields the open-loop transfer function, G(s).
)
1
(
2
)
1
(
1
)
1
(
2
)
1
(
1
4
1
)
1
(
)
(
2
b
t
s
a
t
s
t
s
st
b
a
k2
k1
s
G
+
×
+
+
×
+
×
+
×
×
=
(15)
This transformation produces the best matching at low frequencies
(f < fSAMPLE). At such frequencies (within the closed-loop
bandwidth of the AD2S1210), the transfer function can be
simplified to
2
1
2
1
)
(
st
s
K
s
G
a
+
×
(16)
where:
b
a
k2
k1
K
b
t
a
t
a
×
=
+
=
+
=
)
1
(
)
1
(
2
)
1
(
)
1
(
2
)
1
(
2
1
Table 28. RDC System Response Parameters
Parameter
Description
10-bit resolution
12-bit resolution
14-bit resolution
16-bit resolution
k1 (nominal)
ADC gain
1.8/2.5
k2
Error gain
6 × 106 × 2
π
18 × 106 × 2
π
82 x 106 × 2
π
66 × 106 × 2
π
a
Compensator zero coefficient
8187/8192
4095/4096
8191/8192
32,767/32,768
b
Compensator pole coefficient
509/512
4085/4096
16,359/16,384
32,757/32,768
c
Integrator gain
1/1,024,000
1/4,096,000
1/16,384,000
1/65,536,000
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD2S1210DSTZ | 制造商:Analog Devices 功能描述:IC, ADC, 16BIT, PARALLEL, SERIAL, LQFP-4 |
| AD2S1210SST-EP-RL7 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC IC 10-16 Bit R/D Cnvtr w/Ref Oscilltr RoHS:否 制造商:Analog Devices 通道數(shù)量: 結(jié)構(gòu): 轉(zhuǎn)換速率: 分辨率: 輸入類型: 信噪比: 接口類型: 工作電源電壓: 最大工作溫度: 安裝風(fēng)格: 封裝 / 箱體: |
| AD2S1210SSTZ-EPRL7 | 功能描述:IC CONV R/D VAR REF OSC 48LQFP 制造商:analog devices inc. 系列:* 零件狀態(tài):在售 標(biāo)準(zhǔn)包裝:500 |
| AD2S1210WDSTZ | 制造商:Analog Devices 功能描述: |
| AD2S1210WDSTZRL7 | 功能描述:IC CONV R/D VAR REF OSC 48LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - ADCs/DAC - 專用型 系列:- 產(chǎn)品培訓(xùn)模塊:Data Converter Basics 標(biāo)準(zhǔn)包裝:1 系列:- 類型:電機(jī)控制 分辨率（位）:12 b 采樣率（每秒）:1M 數(shù)據(jù)接口:串行，并聯(lián) 電壓電源:單電源 電源電壓:2.7 V ~ 3.6 V，4.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:100-TQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:剪切帶 (CT) 其它名稱:296-18373-1 |
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