- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄9379 > AD5113BCPZ5-500R7 (Analog Devices Inc)IC DGTL POT 64POS 5K 8LFCSP PDF資料下載
參數(shù)資料
| 型號： | AD5113BCPZ5-500R7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DGTL POT 64POS 5K 8LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 接片： | 64 |
| 電阻（歐姆）： | 5k |
| 電路數(shù)： | 1 |
| 溫度系數(shù)： | 標(biāo)準(zhǔn)值 35 ppm/°C |
| 存儲器類型： | 非易失 |
| 接口： | 3 線串行（芯片選擇，增/減） |
| 電源電壓： | 2.3 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-UFDFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 8-LFCSP-UD（2x2） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | AD5113BCPZ5-500R7DKR |
AD5111/AD5113/AD5115
Data Sheet
Rev. | Page 18 of 24
THEORY OF OPERATION
are designed to operate as true variable resistors for analog
signals within the terminal voltage range of GND < VTERM <
VDD. The resistor wiper position is determined by the RDAC
register contents. The RDAC register acts as a scratchpad
register that allows unlimited changes of resistance settings.
The RDAC register can be programmed with any position
setting using the up/down interface. Once a desirable wiper
position is found, this value can be stored in the EEPROM.
Thereafter, the wiper position is always restored to that position
for subsequent power-up. The storing of EEPROM data takes
approximately 30 ms; during this time, the device is locked and
does not accept any new operation, thus preventing any changes
from taking place.
speed digital control with clock rates up to 50 MHz.
RDAC REGISTER AND EEPROM
The RDAC register directly controls the position of the digital
potentiometer wiper. For example, when the RDAC register is
0x40 (AD5111), the wiper is connected to midscale of the
variable resistor. The RDAC register is a standard logic register;
there is no restriction on the number of changes allowed.
Once a desirable wiper position is found, this value can be
saved into the EEPROM. Thereafter, the wiper position is
always set at that position for any future on-off-on power
supply sequence or recall operation.
BASIC OPERATION
When CS is pulled low, changing the resistance settings is
achieved by clocking the CLK pin. It is negative edge triggered,
and the direction of stepping into the RDAC register is
determined by the state of the U/D input. When a specific state
of the U/D remains, the device continues to change in the same
direction under consecutive clocks until it comes to the end of
the resistance setting. When the wiper reaches the maximum or
minimum setting, additional CLK pulses do not change the
wiper setting. Figure 2 shows a typical increment/decrement
operation.
The U/D pin value can be changed only when the CLK pin
is low.
LOW WIPER RESISTANCE FEATURE
the resistance between terminals. These extra steps are called
bottom scale and top scale. At bottom scale, the typical wiper
resistance decreases from 70 to 45 . At top scale, the
resistance between Terminal A and Terminal W is decreased by
1 LSB and the total resistance is reduced to 70 . The new extra
steps are loaded automatically in the RDAC register after zero-
scale or full-scale position has been reached.
The extra steps are not equal to 1 LSB and are not included in
the INL, DNL, R-INL, and R-DNL specifications.
SHUTDOWN MODE
This feature places Terminal A in open circuit, disconnected
from the internal resistor, and connects Terminal W and
Terminal B. A finite wiper resistance of 45 Ω is present between
these two terminals. The command is sent by a low-to-high
transition on the U/D pin, when CLK is high and CS is enabled.
The command is executed on the CLK negative edge, as shown
shutdown position if any other operation is performed.
EEPROM WRITE OPERATION
allows the wiper position storage. Once a desirable wiper
position is found, this value can be saved into the EEPROM.
Thereafter, the wiper position is always set at that position for
any future power-up sequence or a memory recall operation.
During the storage cycle, the device is locked and does not accept
any new operation, thus preventing any changes from taking
place.
The write cycle is started by applying a pulse in the U/D pin
when CS is enabled and CLK remains high, as shown in
Figure 3. The write cycle takes approximately 20 ms.
A
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ISL12027IV30AZ-T | IC RTC/CALENDAR EEPROM 8-TSSOP |
| ISL12027IV27AZ-T | IC RTC/CALENDAR EEPROM 8-TSSOP |
| VI-2NL-MX-B1 | CONVERTER MOD DC/DC 28V 75W |
| ISL12027IVZ-T | IC RTC/CALENDAR EEPROM 8-TSSOP |
| VI-2NL-MW | CONVERTER MOD DC/DC 28V 100W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD5113BCPZ5-RL7 | 功能描述:IC DGTL POT 64POS 5K SGL 8LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)字電位器 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:DPP 接片:32 電阻（歐姆）:10k 電路數(shù):1 溫度系數(shù):標(biāo)準(zhǔn)值 300 ppm/°C 存儲器類型:非易失 接口:3 線串行（芯片選擇，遞增，增/減） 電源電壓:2.5 V ~ 6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-WFDFN 裸露焊盤 供應(yīng)商設(shè)備封裝:8-TDFN（2x3） 包裝:帶卷 (TR) |
| AD5113BCPZ80-500R7 | 功能描述:IC DGTL POT 64POS 80K 8LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)字電位器 系列:- 標(biāo)準(zhǔn)包裝:3,300 系列:WiperLock™ 接片:257 電阻（歐姆）:100k 電路數(shù):1 溫度系數(shù):標(biāo)準(zhǔn)值 150 ppm/°C 存儲器類型:易失 接口:3 線 SPI（芯片選擇） 電源電壓:1.8 V ~ 5.5 V 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:8-VDFN 裸露焊盤 供應(yīng)商設(shè)備封裝:8-DFN-EP（3x3） 包裝:帶卷 (TR) |
| AD5113BCPZ80-RL7 | 功能描述:IC DGTL POT 64POS 80K SGL 8LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)字電位器 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:DPP 接片:32 電阻（歐姆）:10k 電路數(shù):1 溫度系數(shù):標(biāo)準(zhǔn)值 300 ppm/°C 存儲器類型:非易失 接口:3 線串行（芯片選擇，遞增，增/減） 電源電壓:2.5 V ~ 6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-WFDFN 裸露焊盤 供應(yīng)商設(shè)備封裝:8-TDFN（2x3） 包裝:帶卷 (TR) |
| AD5114 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Single-Channel, 128-/64-/32-Position, Up/Down, ±8% Resistor Tolerance, Nonvolatile Digital Potentiometer |
| AD5114BCPZ10-1-RL7 | 功能描述:IC DGTL POT 32POS 10K SGL 8LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)字電位器 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:DPP 接片:32 電阻（歐姆）:10k 電路數(shù):1 溫度系數(shù):標(biāo)準(zhǔn)值 300 ppm/°C 存儲器類型:非易失 接口:3 線串行（芯片選擇，遞增，增/減） 電源電壓:2.5 V ~ 6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-WFDFN 裸露焊盤 供應(yīng)商設(shè)備封裝:8-TDFN（2x3） 包裝:帶卷 (TR) |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。