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參數(shù)資料
| 型號： | AD5113BCPZ5-500R7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 13/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DGTL POT 64POS 5K 8LFCSP |
| 標準包裝： | 1 |
| 接片： | 64 |
| 電阻（歐姆）： | 5k |
| 電路數(shù)： | 1 |
| 溫度系數(shù)： | 標準值 35 ppm/°C |
| 存儲器類型： | 非易失 |
| 接口： | 3 線串行（芯片選擇，增/減） |
| 電源電壓： | 2.3 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-UFDFN 裸露焊盤，CSP |
| 供應商設備封裝： | 8-LFCSP-UD（2x2） |
| 包裝： | 標準包裝 |
| 其它名稱： | AD5113BCPZ5-500R7DKR |
AD5111/AD5113/AD5115
Data Sheet
Rev. | Page 20 of 24
Similar to the mechanical potentiometer, the resistance of
the RDAC between the W terminal and the A terminal also
produces a digitally controlled complementary resistance, RWA.
RWA starts at the maximum resistance value and decreases as the
data loaded into the latch increases. The general equations for
this operation are
W
AB
AW
R
+
=
Bottom scale (7)
W
AB
AW
R
D
R
+
×
=
128
)
(
From 0 to 127 (8)
TS
AW
R
=
Top scale (9)
W
AB
AW
R
+
=
Bottom scale (10)
W
AB
AW
R
D
R
+
×
=
64
)
(
From 0 to 63 (11)
TS
AW
R
=
Top scale (12)
W
AB
AW
R
+
=
Bottom scale (13)
W
AB
AW
R
D
R
+
×
=
32
)
(
From 0 to 31 (14)
TS
AW
R
=
Top scale (15)
where:
D is the decimal equivalent of the binary code in the 5-/6-/7-bit
RDAC register; 128, 64, and 32 refer to top scale step.
RAB is the end-to-end resistance.
RW is the wiper resistance.
RTS is the wiper resistance at top scale.
Regardless of which setting the part is operating in, take care
to limit the current between A to B, W to A, and W to B, to
the maximum continuous current of ±6 mA (5 k and 10 k)
or ±1.5 mA (80 k), or pulse current specified in Table 6.
Otherwise, degradation or possible destruction of the internal
switch contact can occur.
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates a voltage divider at
W-to-B and W-to-A that is proportional to the input voltage at
GND, which must be positive, current across A-to-B, W-to-A,
and W-to-B can be in either direction.
A
VI
W
B
VO
09654-
045
Figure 44. Potentiometer Mode Configuration
If ignoring the effect of the wiper resistance for simplicity,
connecting Terminal A to 5 V and Terminal B to ground
produces an output voltage at W to B ranging from 0 V to 5 V.
The general equation defining the output voltage at VW with
respect to ground for any valid input voltage applied to
Terminal A and Terminal B, is
B
AB
AW
A
AB
WB
W
V
R
D
R
V
R
D
R
D
V
×
+
×
=
)
(
)
(
)
(
(16)
where:
RWB(D) can be obtained from Equation 1 to Equation 6.
RAW(D) can be obtained from Equation 7 to Equation 14.
Operation of the digital potentiometer in the divider mode
results in a more accurate operation over temperature. Unlike
the rheostat mode, the output voltage is dependent mainly
on the ratio of the internal resistors, RWA and RWB, and not the
absolute values. Therefore, the temperature drift reduces to
5 ppm/°C.
TERMINAL VOLTAGE OPERATING RANGE
ESD diodes for protection. These diodes also set the voltage
boundary of the terminal operating voltages. Positive signals
present on the A, B, or W terminals that exceed VDD are
clamped by the forward-biased diode. There is no polarity
constraint between VA, VW, and VB, but they cannot be higher
than VDD or lower than GND.
A
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