參數(shù)資料
型號: AD5114BCPZ80-500R7
廠商: Analog Devices Inc
文件頁數(shù): 17/28頁
文件大小: 0K
描述: IC DGTL POT 32POS 80K 8LFCSP
標(biāo)準(zhǔn)包裝: 1
接片: 32
電阻(歐姆): 80k
電路數(shù): 1
溫度系數(shù): 標(biāo)準(zhǔn)值 35 ppm/°C
存儲器類型: 非易失
接口: I²C,2 線串口
電源電壓: 1.8 V ~ 5 V,2.3 V ~ 5.5V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 8-UFDFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 8-LFCSP-UD(2x2)
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: AD5114BCPZ80-500R7DKR
AD5110/AD5112/AD5114
Data Sheet
Rev. B | Page 24 of 28
RDAC ARCHITECTURE
To achieve optimum performance, Analog Devices, Inc., has
patented the RDAC segmentation architecture for all the digital
potentiometers. In particular, the AD5110/AD5112/AD5114
employ a two-stage segmentation approach as shown in
designed with the transmission gate CMOS topology and with
the gate voltage derived from VDD.
RL
RS
W
RS
A
B
BS
6-BIT/7-BIT/8-BIT
ADDRESS
DECODER
TS
09582-
046
Figure 46. AD5110/AD5112/AD5114 Simplified RDAC Circuit
Top Scale/Bottom Scale Architecture
In addition, the AD5110/AD5112/AD5114 include a new
feature to reduce the resistance between terminals. These extra
steps are called bottom scale and top scale. At bottom scale, the
typical wiper resistance decreases from 70 to 45 . At top
scale, the resistance between Terminal A and Terminal W is
decreased by 1 LSB, and the total resistance is reduced to 70 .
The extra steps are not equal to 1 LSB and are not included in
the INL, DNL, R-INL, and R-DNL specifications.
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation—±8% Resistor Tolerance
The AD5110/AD5112/AD5114 operate in rheostat mode when
only two terminals are used as a variable resistor. The unused
terminal can be floating or tied to the Terminal W as shown in
A
W
B
A
W
B
A
W
B
09582-
047
Figure 47. Rheostat Mode Configuration
The nominal resistance between Terminal A and Terminal B,
RAB, is available in 5 kΩ, 10 kΩ, and 80 kΩ and has 32/64/128
tap points accessed by the wiper terminal. The 5-/6-/7-bit data
in the RDAC latch is decoded to select one of the 32/64/128
possible wiper settings. The general equations for determining
the digitally programmed output resistance between the W
terminal and B terminal are
BS
WB
R
R =
Bottom scale (0xFF) (1)
W
AB
WB
R
D
R
+
×
=
128
)
(
From 0x00 to 0x80 (2)
BS
WB
R
R =
Bottom scale (0xFF) (3)
W
AB
WB
R
D
R
+
×
=
64
)
(
From 0x00 to 0x40 (4)
BS
WB
R
R =
Bottom scale (0xFF) (5)
W
AB
WB
R
D
R
+
×
=
32
)
(
From 0x00 to 0x20 (6)
where:
D is the decimal equivalent of the binary code in the 5-/6-/7-bit
RDAC register.
RAB is the end-to-end resistance.
RW is the wiper resistance.
RBS is the wiper resistance at bottom scale
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