VLOGIC
參數(shù)資料
型號: AD5114BCPZ80-500R7
廠商: Analog Devices Inc
文件頁數(shù): 28/28頁
文件大小: 0K
描述: IC DGTL POT 32POS 80K 8LFCSP
標(biāo)準(zhǔn)包裝: 1
接片: 32
電阻(歐姆): 80k
電路數(shù): 1
溫度系數(shù): 標(biāo)準(zhǔn)值 35 ppm/°C
存儲器類型: 非易失
接口: I²C,2 線串口
電源電壓: 1.8 V ~ 5 V,2.3 V ~ 5.5V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 8-UFDFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 8-LFCSP-UD(2x2)
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: AD5114BCPZ80-500R7DKR
Data Sheet
AD5110/AD5112/AD5114
Rev. B | Page 9 of 28
INTERFACE TIMING SPECIFICATIONS
VLOGIC = 1.8 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 5.
Parameter1
Test Conditions/
Comments
Min
Typ
Max
Unit
Description
f
Standard mode
100
kHz
Serial clock frequency
Fast mode
400
kHz
t
1
Standard mode
4.0
s
t
HIGH, SCL high time
Fast mode
0.6
s
t
2
Standard mode
4.7
s
t
LOW, SCL low time
Fast mode
1.3
s
t
3
Standard mode
250
ns
t
SU;DAT, data setup time
Fast mode
100
ns
t
4
Standard mode
0
3.45
s
t
HD;DAT, data hold time
Fast mode
0
0.9
s
t
5
Standard mode
4.7
s
t
SU;STA, setup time for a repeated start condition
Fast mode
0.6
s
t
6
Standard mode
4
s
t
HD;STA, hold time (repeated) start condition
Fast mode
0.6
s
t
7
Standard mode
4.7
s
t
BUF, bus free time between a stop and a start
condition
Fast mode
1.3
s
t
8
Standard mode
4
s
t
SU;STO, setup time for stop condition
Fast mode
0.6
s
t
9
Standard mode
1000
ns
t
RDA, rise time of SDA signal
Fast mode
20 + 0.1 C
L
300
ns
t
10
Standard mode
300
ns
t
FDA, fall time of SDA signal
Fast mode
20 + 0.1 C
L
300
ns
t
11
Standard mode
1000
ns
t
RCL, rise time of SCL signal
Fast mode
20 + 0.1 C
L
300
ns
t
11A
Standard mode
1000
ns
t
RCL1, rise time of SCL signal after a repeated start
condition and after an acknowledge bit.
Fast mode
20 + 0.1 C
L
300
ns
t
12
Standard mode
300
ns
t
FCL, fall time of SCL signal
Fast mode
20 + 0.1 C
L
300
ns
Fast mode
0
50
ns
Pulse width of suppressed spike
tEEPROM_PROGRAM4
15
50
ms
Memory program time
t
POWER_UP
50
s
Power-on EEPROM restore time
t
RESET
25
s
Reset EEPROM restore time
1 Maximum bus capacitance is limited to 400 pF.
2 The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate but has a negative effect on EMC behavior
of the part.
3 Input filtering on the SCL and SDA inputs suppress noise spikes that are less than 50 ns for fast mode.
4 EEPROM program time depends on the temperature and EEPROM write cycles. Higher timing is expected at a lower temperature and higher write cycles.
5 Maximum time after V
DD is equal to 2.3 V.
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