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參數(shù)資料
| 型號(hào)： | AD5171EVAL |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 數(shù)字電位計(jì) |
| 英文描述： | 64-Position OTP Digital Potentiometer |
| 中文描述： | 64工位檢察官數(shù)字電位器 |
| 文件頁(yè)數(shù)： | 12/20頁(yè) |
| 文件大?。?/td> | 1722K |
| 代理商： | AD5171EVAL |
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AD5171
Table 5. R
WB
vs. Codes; R
AB
= 10 k
and
the A Terminal Is Opened
D (Dec)
R
WB
()
63
10060
32
5139
1
219
0
60
Output State
Full-Scale (R
AB
+ R
W
)
Midscale
1 LSB
Zero-Scale (Wiper Contact Resistance)
Since a finite wiper resistance of 60 is present in the zero-
scale condition, care should be taken to limit the current flow
between W and B in this state to a maximum pulse current of
no more than 20 mA. Otherwise, degradation or possible
destruction of the internal switch contact can occur.
Similar to the mechanical potentiometer, the resistance of the
RDAC between the wiper W and terminal A also produces a
complementary resistance R
WA
. When these terminals are used,
the B terminal can be opened or shorted to W. Setting the
resistance value for R
WA
starts at a maximum value of resistance
and decreases as the data loaded in the latch increases in value.
The general equation for this operation is
W
R
AB
R
D
D
WA
R
+
×
=
63
63
)
(
(2)
D
63
Table 6. R
WA
vs. Codes; R
AB
=10 k
and
B Terminal Is Opened
D (Dec)
R
WA
()
63
60
32
4980
1
9901
0
10060
Output State
Full-Scale
Midscale
1 LSB
Zero-Scale
The typical distribution of the resistance tolerance from device
to device is process lot dependent, and it is possible to have
±30% tolerance.
D5
D4
D3
D2
D1
D0
RDAC
LATCH
AND
DECODER
R
S
R
S
R
S
A
W
B
0
Figure 26. AD5171 Equivalent RDAC Circuit
Potentiometer Mode Operation
If all three terminals are used, the operation is called the
potentiometer mode. The most common configuration is the
voltage divider operation (Figure 27).
A
V
I
W
B
V
O
0
Figure 27. Potentiometer Mode Configuration
Ignoring the effect of the wiper resistance, the
transfer function
is simply
A
W
V
D
63
D
V
)
(
=
(3)
A more accurate calculation, which includes the wiper
resistance effect, yields
A
W
W
AB
W
V
R
R
R
D
V
2
R
)
(
AB
+
+
=
(4)
Unlike in rheostat mode operation where the absolute tolerance
is high, potentiometer mode operation yields an almost ratio-
metric function of
D/63
with a relatively small error contributed
by the R
W
terms, and
therefore the tolerance effect is almost
cancelled. Although the thin film step resistor R
S
and CMOS
switches resistance R
W
have very different temperature coefficients,
the ratio-metric adjustment also reduces the overall temperature
coefficient effect to 5 ppm/
o
C, except at low value codes where R
W
dominates.
Potentiometer mode operations include others such as op amp
input, feedback resistor networks, and other voltage scaling
applications. A, W, and B terminals can in fact be input or output
terminals provided that |V
AB
|, |V
WA
|, and |V
WB
| do not exceed
V
DD
to GND.
ESD PROTECTION
Digital inputs SDA and SCL are protected with a series input
resistor and parallel Zener ESD structures (Figure 28).
LOGIC
340
0
Figure 28. ESD Protection of Digital Pins
Rev. PrC | Page 12 of 20
Preliminary Technical Data
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