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參數(shù)資料
| 型號： | AD5171EVAL |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 數(shù)字電位計 |
| 英文描述： | 64-Position OTP Digital Potentiometer |
| 中文描述： | 64工位檢察官數(shù)字電位器 |
| 文件頁數(shù)： | 16/20頁 |
| 文件大?。?/td> | 1722K |
| 代理商： | AD5171EVAL |
AD5171
this stage, all other devices on the bus remain idle while the
selected device waits for data to be written to or read from
its serial register.
2.
The write operation contains one more instruction byte
than the read operation. The instruction byte in the write
mode follows the slave address byte. The MSB of the
instruction byte labeled T is the one-time programming
bit. After acknowledging the instruction byte, the last byte
in the write mode is the data byte. Data is transmitted over
the serial bus in sequences of nine clock pulses (eight data
bits followed by an Acknowledge bit). The transitions on
the SDA line must occur during the low period of SCL and
remain stable during the high period of SCL (Figure 36).
3.
In the read mode, the data byte follows immediately after
the acknowledgment of the slave address byte. Data is
transmitted over the serial bus in sequences of nine clock
pulses (slight difference with the write mode; there are
eight data bits followed by a No Acknowledge bit).
Similarly, the transitions on the SDA line must occur
during the low period of SCL and remain stable during the
high period of SCL (Figure 38).
4.
When all data bits have been read or written, a stop
condition is established by the master. A stop condition is
defined as a low-to-high transition on the SDA line while
SCL is high. In the write mode, the master will pull the
SDA line high during the 10
th
clock pulse to establish a stop
condition (Figure 36 and Figure 37). In the read mode, the
master will issue a No Acknowledge for the 9
th
clock pulse,
i.e., the SDA line remains high. The master will then bring
the SDA line low before the 10
th
clock pulse, which goes
high to establish a stop condition (Figure 38).
A repeated write function gives the user flexibility to update the
RDAC output a number of times, except after permanent
programming, addressing, and instructing the part only once.
During the write cycle, each data byte will update the RDAC
output. For example, after the RDAC has acknowledged its slave
address and instruction bytes, the RDAC output will update
after these two bytes. If another byte is written to the RDAC
while it is still addressed to a specific slave device with the same
instruction, this byte will update the output of the selected slave
device. If different instructions are needed, the write mode has
to be started with a new slave address, instruction, and data
bytes. Similarly, a repeated read function of the RDAC is also
allowed.
CONTROLLING TWO DEVICES ON ONE BUS
Figure 39 shows two AD5171 devices on the same serial bus.
Each has a different slave address since the state of each AD0
pin is different. This allows each device to be operated
independently. The master device output bus line drivers are
open-drain pull-downs in a fully I
2
C compatible interface.
MASTER
SDA SCL
AD0
AD5171
SDA SCL
AD0
AD5171
SDA
SCL
5V
Rp
Rp
5V
0
Figure 39. Two AD5171 Devices on One Bus
Rev. PrC | Page 16 of 20
Preliminary Technical Data
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