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參數(shù)資料
| 型號： | AD5172EVAL1 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 通用總線功能 |
| 英文描述： | Dual, 256-Tap, Nonvolatile, I2C-Interface, Digital Potentiometers |
| 中文描述： | 雙路、256抽頭、非易失、I2C接口、數(shù)字電位器 |
| 文件頁數(shù)： | 20/24頁 |
| 文件大?。?/td> | 948K |
| 代理商： | AD5172EVAL1 |
AD5172/AD5173
I
2
C COMPATIBLE 2-WIRE SERIAL BUS
The 2-wire I
2
C serial bus protocol operates as follows:
Rev. A | Page 20 of 24
1.
The master initiates data transfer by establishing a START
condition, which is when a high-to-low transition on the
SDA line occurs while SCL is high (see Figure 50 and
Figure 51). The following byte is the slave address byte,
which consists of the slave address followed by an R/W bit
(this bit determines whether data is read from or written to
the slave device). The AD5172 has a fixed slave address
byte, whereas the AD5173 has two configurable address
bits, AD0 and AD1 (see Figure 50 and Figure 51).
The slave whose address corresponds to the transmitted
address responds by pulling the SDA line low during the
ninth clock pulse (this is termed the acknowledge bit). At
this stage, all other devices on the bus remain idle while the
selected device waits for data to be written to or read from
its serial register. If the R/W bit is high, the master reads
from the slave device. If the R/W bit is low, the master
writes to the slave device.
2.
In the write mode, the second byte is the instruction byte.
The first bit (MSB) of the instruction byte is the RDAC
subaddress select bit. A logic low selects channel 1; a logic
high selects channel 2.
The second MSB, SD, is a shutdown bit. A logic high causes
an open circuit at terminal A while shorting the wiper to
terminal B. This operation yields almost 0 in rheostat
mode or 0 V in potentiometer mode. It is important to note
that the shutdown operation does not disturb the contents
of the register. When brought out of shutdown, the previ-
ous setting is applied to the RDAC. Also, during shutdown,
new settings can be programmed. When the part is
returned from shutdown, the corresponding VR setting is
applied to the RDAC.
The third MSB, T, is the OTP programming bit. A logic
high blows the poly fuses and programs the resistor setting
permanently.
The fourth MSB must always be at Logic 0.
The fifth MSB, OW, is an overwrite bit. When raised to a
logic high, OW allows the RDAC setting to be changed
even after the internal fuses have been blown. However,
once OW is returned to a logic zero, the position of the
RDAC returns to the setting prior to overwrite. Because
OW is not static, if the device is powered off and on, the
RDAC presets to midscale or to the setting at which the
fuses were blown, depending on whether or not the fuses
have been permanently set already.
The remainder of the bits in the instruction byte are don’t
cares (see Figure 50 and Figure 51).
After acknowledging the instruction byte, the last byte in
write mode is the data byte. Data is transmitted over the
serial bus in sequences of nine clock pulses (eight data bits
followed by an acknowledge bit). The transitions on the
SDA line must occur during the low period of SCL and
remain stable during the high period of SCL (see
Figure 49).
3.
In the read mode, the data byte follows immediately after
the acknowledgment of the slave address byte. Data is
transmitted over the serial bus in sequences of nine clock
pulses (a slight difference from the write mode, where there
are eight data bits followed by an acknowledge bit). Simi-
larly, the transitions on the SDA line must occur during the
low period of SCL and remain stable during the high
period of SCL (see Figure 52 and Figure 53).
Note that the channel of interest is the one that is
previously selected in the write mode. In the case where
users need to read the RDAC values of both channels, they
must program the first channel in the write mode and then
change to the read mode to read the first channel value.
After that, the user must change back to the write mode
with the second channel selected and read the second
channel value in the read mode. It is not necessary for users
to issue the Frame 3 data byte in the write mode for subse-
quent readback operation. Refer to Figure 52 and Figure 53
for the programming format.
Following the data byte, the validation byte contains two
validation bits, E0 and E1. These bits signify the status of
the one-time programming (see Figure 52 and Figure 53).
4.
After all data bits have been read or written, a STOP
condition is established by the master. A STOP condition is
defined as a low-to-high transition on the SDA line while
SCL is high. In write mode, the master pulls the SDA line
high during the 10
th
clock pulse to establish a STOP
condition (see Figure 50 and Figure 51). In read mode, the
master issues a No Acknowledge for the ninth clock pulse
(i.e., the SDA line remains high). The master then brings
the SDA line low before the 10
th
clock pulse, which goes
high to establish a STOP condition (see Figure 52 and
Figure 53).
A repeated write function gives the user flexibility to update the
RDAC output a number of times after addressing and instruc-
ting the part only once. For example, after the RDAC has
acknowledged its slave address and instruction bytes in the
write mode, the RDAC output is updated on each successive
byte. If different instructions are needed, the write/read mode
has to start again with a new slave address, instruction, and data
byte. Similarly, a repeated read function of the RDAC is also
allowed.
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