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| 型號(hào)： | AD5207BRUZ10-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 2/16頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DGTL POT DUAL 10K 14-TSSOP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 接片： | 256 |
| 電阻（歐姆）： | 10k |
| 電路數(shù)： | 2 |
| 溫度系數(shù)： | 標(biāo)準(zhǔn)值 500 ppm/°C |
| 存儲(chǔ)器類(lèi)型： | 易失 |
| 接口： | 4 線 SPI（芯片選擇） |
| 電源電壓： | 2.7 V ~ 5.5 V，±2.2 V ~ 2.7 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 14-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 14-TSSOP |
| 包裝： | 帶卷 (TR) |
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REV. 0
AD5207
–10–
The data setup and data hold times in the specification table
determine the data valid time requirements. The last ten bits of
the data word entered into the serial register are held when
CS
returns high and any extra bits are ignored. At the same time, when
CS goes high, it gates the address decoder enabling one of two
positive edge-triggered AD5207 RDAC latches; see Figure 5 detail.
SDI
CLK
CS
CK RS
D
Q
SERIAL
REGISTER
SDO
SHDN
INTERNAL
RS
Figure 4. Detail SDO Output Schematic of the AD5207
The target RDAC latch is loaded with the last eight bits of the
data word to complete one RDAC update. For AD5207, it
cannot update both channels simultaneously and therefore, two
separate 10-bit data words must be clocked in to change both
VR settings.
RDAC1
RDAC2
ADDR
DECODE
SERIAL
REGISTER
AD5207
SDI
CLK
CS
Figure 5. Equivalent Input Control Logic
All digital inputs are protected with a series input resistor and
parallel Zener ESD structure shown in Figures 6 and 7. Applies
to digital input pins
CS, SDI, SDO, SHDN, and CLK. Digital
input level for Logic 1 can be anywhere from 2.4 V to 5 V
regardless of whether it is in single or dual supplies.
340
VSS
LOGIC
DIGITAL PIN
Figure 6. ESD Protection of Digital Pins
A,B,W
VSS
Figure 7. ESD Protection of Resistor Terminals
D7
D6
D5
D4
D3
D2
D1
D0
RDAC
LATCH
AND
DECODER
RS
SHDN
Ax
Wx
Bx
Figure 8. Equivalent RDAC Circuit
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation
The nominal resistance of the RDAC between Terminals A and
B is available with values of 10 k
, 50 k, and 100 k. The last
few digits of the part number determine the nominal resistance
value, e.g., 10 k
= 10; 50 k = 50; and 100 k = 100. The
nominal resistance (RAB) of the VR has 256 contact points
accessed by the wiper terminal, plus the B Terminal contact.
The 8-bit data in the RDAC latch is decoded to select one of
the 256 possible settings. Assume a 10 k
part is used, the
wiper’s first connection starts at the B Terminal for data 00H.
Since there is a 45
wiper contact resistance, such connection
yields a minimum of 45
resistance between Terminals W and
B. The second connection is the first tap point corresponds to
84
(R
WB = RAB/256 + RW = 39
+ 45 ) for data 01
H. The
third connection is the next tap point representing 123
(39 ×
2 + 45) for data 02H and so on. Each LSB value increase moves
the wiper up the resistor ladder until the last tap point is reached at
10006
(RAB – 1 LSB + RW). Figure 8 shows a simplified dia-
gram of the equivalent RDAC circuit.
The general equation determining the programmable output
resistance between W and B is:
RD
D
RR
WB
AB
W
() =×
+
256
(1)
where D is the data contained in the 8-bit RDAC latch, and RAB
is the nominal end-to-end resistance.
For example, RAB =10 k
, A Terminal can be open-circuit or
tied to W. The following output resistance RWB will be set for
the following RDAC latch codes.
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