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參數(shù)資料
| 型號： | AD5207BRUZ100-R7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 3/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC POT DGTL DUAL 256POS 14TSSOP |
| 標準包裝： | 1,000 |
| 接片： | 256 |
| 電阻（歐姆）： | 100k |
| 電路數(shù)： | 2 |
| 溫度系數(shù)： | 標準值 500 ppm/°C |
| 存儲器類型： | 易失 |
| 接口： | 4 線 SPI（芯片選擇） |
| 電源電壓： | 2.7 V ~ 5.5 V，±2.2 V ~ 2.7 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 14-TSSOP |
| 包裝： | 帶卷 (TR) |
REV. 0
AD5207
–11–
Table IV.
DRWB
(DEC)
( )
Output State
255
10006
Full-Scale (RAB – 1 LSB + RW)
128
5045
Midscale
184
1 LSB
0
45
Zero-Scale (Wiper Contact Resistance)
Note that in the zero-scale condition a finite wiper resistance of
45
is present. Care should be taken to limit the current flow
between W and B in this state to a maximum current of no more
than 5 mA. Otherwise, degradation or possibly destruction of
the internal switch contacts can occur.
Similar to the mechanical potentiometer, the resistance of the
RDAC between the wiper W and Terminal A also produces a
digitally controlled resistance RWA. When these terminals are used,
the B Terminal should be let open or tied to the wiper terminal.
Setting the resistance value for RWA starts at a maximum value
of resistance and decreases as the data loaded in the latch is
increased in value. The general equation for this operation is:
RD
D
RR
WA
AB
W
() =×
+
256
–
(2)
For example, when RAB = 10 k
, B terminal is either open or
tied to W, the following output resistance, RWA, will be set for
the following RDAC latch codes.
Table V.
DRWA
(DEC)
( )
Output State
255
84
Full-Scale (RAB/256 + RW)
128
5045
Midscale
1
10006
1 LSB
0
10045
Zero-Scale
The typical distribution of RAB from channel to channel matches
within
±1%. Device-to-device matching is process-lot depen-
dent and is possible to have
±30% variation. The change in RAB
with temperature has a 500 ppm/
°C temperature coefficient.
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates an output voltage
proportional to the input voltage. Let’s ignore the effect of
the wiper resistance for the moment. For example, when con-
necting A Terminal to 5 V and B Terminal to ground, it produces
a programmable output voltage at the wiper starting at zero
volts up to 1 LSB less than 5 V. Each LSB of voltage is equal
to the voltage applied across terminal AB divided by the 256
position of the potentiometer divider. Since AD5207 is capable
for dual supplies, the general equation defining the output volt-
age with respect to ground for any given input voltage applied to
terminals AB is:
VD
D
V
D
V
WA
B
() =+
256
(3)
Operation of the digital potentiometer in the divider mode
results in more accurate operation over temperature. Unlike the
rheostat mode, the output voltage is dependent on the ratio of
RWA and RWB and not the absolute values; therefore, the drift
reduces to 15 ppm/
°C. There is no voltage polarity constraint
between Terminals A, B, and W as long as the terminal voltage
stays within VSS < VTERM < VDD.
RDAC CIRCUIT SIMULATION MODEL
The internal parasitic capacitances and the external capacitive
loads dominate the ac characteristics of the RDACs. Config-
ured as a potentiometer divider the –3 dB bandwidth of the
AD5207BRU10 (10 k
resistor) measures 600 kHz at half
scale. TPC 16 provides the large signal BODE plot characteris-
tics of the three available resistor versions 10 k
and 50 k.
The gain flatness versus frequency graph, TPC 16, predicts
filter applications performance. A parasitic simulation model has
been developed and is shown in Figure 9. Listing I provides a
macro model net list for the 10 k
RDAC:
CW
70pF
CB
CA
B
A
RDAC
10k
W
CB = 45pF
CA = 45pF
Figure 9. RDAC Circuit Simulation Model for RDAC = 10 k
Listing I. Macro Model Net List for RDAC
.PARAM D=255, RDAC=10E3
*
.SUBCKT DPOT (A,W)
*
CA A 0 45E-12
RAW A W {(1-D/256)
*RDAC+50}
CW W 0 70E-12
RBW W B {D/256
*RDAC+50}
CB B 0 45E-12
*
.ENDS DPOT
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