參數(shù)資料
型號(hào)： AD5207BRUZ50-RL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 16/16頁(yè)
文件大?。?/td> 0K
描述： IC DGTL POT DUAL 50K 14-TSSOP
標(biāo)準(zhǔn)包裝： 1,000
接片： 256
電阻（歐姆）： 50k
電路數(shù)： 2
溫度系數(shù)： 標(biāo)準(zhǔn)值 500 ppm/°C
存儲(chǔ)器類型： 易失
接口： 4 線 SPI（芯片選擇）
電源電壓： 2.7 V ~ 5.5 V，±2.2 V ~ 2.7 V
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 14-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 14-TSSOP
包裝： 帶卷 (TR)
REV. 0
AD5207
–9–
OPERATION
The AD5207 provides a dual channel, 256-position digitally
controlled variable resistor (VR) device. The terms VR, RDAC,
and digital potentiometer are sometimes used interchangeably.
Changing the programmable VR settings is accomplished by
clocking in a 10-bit serial data word into the SDI (Serial Data
Input) pin. The format of this data word is two address Bits, A1
and A0. With A1 and A2 are first and second bits respectively,
followed by eight data bits B7–B0 with MSB first. Table I pro-
vides the serial register data word format. See Table III for the
AD5207 address assignments to decode the location of VR latch
receiving the serial register data in Bits B7 through B0. VR settings
can be changed one at a time in random sequence. The AD5207
presets to a midscale during power-on condition. AD5207 contains
a power shutdown
SHDN pin. When activated in logic low.
Terminals A on both RDACs will be open-circuited while the
wiper terminals WX are shorted to BX. As a result, a minimum
amount of leakage current will be consumed in both RDACs,
and the power dissipation is negligible. During the shutdown
mode, the VR latch settings are maintained. Thus the previ-
ous resistance values remain when the devices are resumed
from the shutdown.
DIGITAL INTERFACING
The AD5207 contains a standard three-wire serial input control
interface. The three inputs are clock (CLK), chip select (
CS),
and serial data input (SDI). The positive edge-sensitive CLK
input requires clean transitions to avoid clocking incorrect data
into the serial input register. Standard logic families work well.
If mechanical switches are used for product evaluation, they
should be debounced by a flip-flop or other suitable means. Fig-
ure 2 shows more detail of the internal digital circuitry. When
CS
is low, the clock loads data into the serial register on each posi-
tive clock edge; see Table II.
SER
REG
A0
D7
D6
D5
D4
D3
D2
D1
D0
ADDR
DEC
EN
RDAC
LATCH
#2
RDAC
LATCH
#1
AD5207
POWER-ON RESET
SHDN
VDD
A1
W1
B1
A2
W2
B2
VSS
CS
CLK
SDO
SDI
Figure 2. Block Diagram
The serial-data-output (SDO) pin contains an open drain
n-channel FET. This output requires a pull-up resistor in order
to transfer data to the next package’s SDI pin. The pull-up
resistor termination voltage may be larger than the VDD supply
of the AD5207 SDO output device, e.g., the AD5207 could
operate at VDD = 3.3 V and the pull-up for interface to the next
device could be set at 5 V. This allows for daisy chaining several
RDACs from a single processor serial-data line. The clock period
may need to be increased when using a pull-up resistor to the
SDI pin of the following devices in series. Capacitive loading at
the daisy chain node SDO–SDI between devices may add time
delay to subsequent devices. User should be aware of this poten-
tial problem in order to successfully achieve data transfer. See
Figure 3. When configuring devices for daisy-chaining, the
CS
should be kept low until all the bits of every package are clocked
into their respective serial registers, ensuring that the address bit
and data bits are in the proper decoding location. This requires
20 bits of address and data complying with the data word in
Table I if two AD5207 RDACs are daisy chained. During shut-
down
SHDN, the SDO output pin is forced to OFF (logic high
state) to disable power dissipation in the pull-up resistor. See
Figure 4 for equivalent SDO output circuit schematic.
RP
2k
AD5207
SDO
SDI
CLK
CS
AD5207
SDO
SDI
CLK
CS
C
+V
Figure 3. Daisy-Chain Configuration Using SDO
Table II. Input Logic Control Truth Table
CLK
CS
SHDN
Register Activity
L
H
No SR effect, enables SDO pin.
P
L
H
Shift one bit in from the SDI pin. MSB
first. The tenth previously entered bit
is shifted out of the SDO pin.
X
P
H
Load SR data into RDAC latch based
on A0 decode (Table III).
X
H
No Operation.
X
H
L
Open circuits all resistor A Terminals,
connects W to B, turns off SDO out-
put transistor.
NOTE
P = positive edge, X = don’t care, SR = shift register.
Table III. Address Decode Table
A1
A0
Latch Loaded
0
RDAC #1
0
1
RDAC #2
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