參數(shù)資料
型號(hào)： AD5220BRM100
廠商： Analog Devices Inc
文件頁數(shù)： 4/11頁
文件大?。?/td> 0K
描述： IC DGTL POT SNGL 128POS 8USOIC
標(biāo)準(zhǔn)包裝： 50
接片： 128
電阻（歐姆）： 100k
電路數(shù)： 1
溫度系數(shù)： 標(biāo)準(zhǔn)值 800 ppm/°C
存儲(chǔ)器類型： 易失
接口： 4 線串行（芯片選擇，遞增，增/減）
電源電壓： 2.7 V ~ 5.5 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 8-TSSOP，8-MSOP（0.118"，3.00mm 寬）
供應(yīng)商設(shè)備封裝： 8-MSOP
包裝： 管件
–2–
REV.
AD5220–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Parameter
Symbol
Conditions
Min
Typ
1
Max
Units
DC CHARACTERISTICS RHEOSTAT MODE Specifications Apply to All VRs
Resistor Differential NL2
R-DNL
RWB, VA = NC, RAB = 10 k
–1
±0.4
+1
LSB
RWB, VA = NC, RAB = 50 k or 100 k
–0.5
±0.1
+0.5
LSB
Resistor Nonlinearity
2
R-INL
RWB, VA = NC, RAB = 10 k
–1
±0.5
+1
LSB
RWB, VA = NC, RAB = 50 k or 100 k
–0.5
±0.1
+0.5
LSB
Nominal Resistor Tolerance
RT
A = +25°C
–30
+30
%
Resistance Temperature Coefficient
R
AB/TVAB = VDD, Wiper = No Connect
800
ppm/
°C
Wiper Resistance
RW
IW = VDD/R, VDD = +3 V or +5 V
40
100
DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Specifications Apply to All VRs
Resolution
N
7
Bits
Integral Nonlinearity3
INL
RAB = 10 k
–1
±0.5
+1
LSB
RAB = 50 k, 100 k
–0.5
±0.2
+0.5
LSB
Differential Nonlinearity Error
3
DNL
RAB = 10 k
–1
±0.4
+1
LSB
RAB = 50 k, 100 k
–0.5
±0.1
+0.5
LSB
Voltage Divider Temperature Coefficient
V
W/T
Code = 40H
20
ppm/
°C
Full-Scale Error
VWFSE
Code = 7FH
–2
–0.5
0
LSB
Zero-Scale Error
VWZSE
Code = 00H
0
+0.5
+1
LSB
RESISTOR TERMINALS
Voltage Range
4
VA, VB, VW
0VDD
V
Capacitance5 A, B
CA, CB
f = 1 MHz, Measured to GND, Code = 40H
10
pF
Capacitance
5 WC
W
f = 1 MHz, Measured to GND, Code = 40H
48
pF
Common-Mode Leakage
ICM
VA = VB = VW
7.5
nA
DIGITAL INPUTS AND OUTPUTS
Input Logic High
VIH
VDD = +5 V/+3 V
2.4/2.1
V
Input Logic Low
VIL
VDD = +5 V/+3 V
0.8/0.6
V
Input Current
IIL
VIN = 0 V or +5 V
±1
A
Input Capacitance
5
CIL
5pF
POWER SUPPLIES
Power Supply Range
VDD
2.7
5.5
V
Supply Current
IDD
VIH = +5 V or VIL = 0 V, VDD = +5 V
15
40
A
Power Dissipation6
PDISS
VIH = +5 V or VIL = 0 V, VDD = +5 V
75
200
W
Power Supply Sensitivity
PSS
0.004
0.015
%/%
DYNAMIC CHARACTERISTICS
5, 7, 8
Bandwidth –3 dB
BW_10K
RAB = 10 k, Code = 40H
650
kHz
BW_50K
RAB = 50 k, Code = 40H
142
kHz
BW_100K
RAB = 100 k, Code = 40H
69
kHz
Total Harmonic Distortion
THDW
VA =1 V rms + 2.5 V dc, VB = 2.5 V dc, f = 1 kHz
0.002
%
VW Settling Time
tS
VA = VDD, VB = 0 V, 50% of Final Value,
10K/50K/100K
0.6/3/6
s
Resistor Noise Voltage
eNWB
RWB = 5 k, f = 1 kHz
14
nV/
√Hz
INTERFACE TIMING CHARACTERISTICS Applies to All Parts
5, 9
Input Clock Pulsewidth
tCH, tCL
Clock Level High or Low
25
ns
CS to CLK Setup Time
tCSS
20
ns
CS Rise to Clock Hold Time
tCSH
20
ns
U/D to Clock Fall Setup Time
tUDS
10
ns
NOTES
1Typicals represent average readings at +25
°C and V
DD = +5 V.
2Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 29 test circuit.
3INL and DNL are measured at V
W with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V A = VDD and VB = 0 V.
DNL specification limits of
± 1 LSB maximum are guaranteed monotonic operating conditions. See Figure 28 test circuit.
4Resistor terminals A, B, W have no limitations on polarity with respect to each other.
5Guaranteed by design and not subject to production test.
6P
DISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
7Bandwidth, noise and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest band-
width. The highest R value results in the minimum overall power consumption.
8All dynamic characteristics use V
DD = +5 V.
9See timing diagrams for location of measured values. All input control voltages are specified with t
R = tF = 1 ns (10% to 90% of VDD) and timed from a voltage level
of 1.6 V. Switching characteristics are measured using both VDD = +3 V or +5 V.
Specifications subject to change without notice.
(VDD = +3 V
10% or +5 V
10%, VA = +VDD, VB = 0 V, –40 C < TA < +85 C unless
otherwise noted)
A
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