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參數(shù)資料
| 型號(hào)： | AD5227BUJZ50-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DGTL POT 50K UP/DN TSOT23-8 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 接片： | 64 |
| 電阻（歐姆）： | 50k |
| 電路數(shù)： | 1 |
| 溫度系數(shù)： | 標(biāo)準(zhǔn)值 35 ppm/°C |
| 存儲(chǔ)器類型： | 易失 |
| 接口： | 3 線串行（芯片選擇，增/減） |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SOT-23-8 薄型，TSOT-23-8 |
| 供應(yīng)商設(shè)備封裝： | TSOT-23-8 |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | AD5227BUJZ50-RL7DKR |
AD5227
Rev. B | Page 4 of
16
Parameter
Conditions
Min
Max
Unit
INTERFACE TIMING CHARACTERISTICS (applies to all parts6, 10)
Clock Frequency
fCLK
50
MHz
Input Clock Pulse Width
tCH, tCL
Clock level high or low
10
ns
CS to CLK Setup Time
tCSS
10
ns
CS Rise to CLK Hold Time
tCSH
10
ns
U/D to Clock Fall Setup Time
tUDS
10
ns
1 Typicals represent average readings at 25°C, VDD = 5 V.
2 Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3 NL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.
4 DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
5 Resistor Terminals A, B, W have no limitations on polarity with respect to each other.
6 Guaranteed by design and not subject to production test.
7 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
8 Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest
bandwidth. The highest R value results in the minimum overall power consumption.
9 All dynamic characteristics use VDD = V.
10 All input control voltages are specified with tR = tF = 1 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. Switching characteristics are measured using
VDD = 5 V.
INTERFACE TIMING DIAGRAMS
04419-0-004
CS = LOW
U/D = HIGH
CLK
RWB
Figure 2. Increment RWB
04419-0-005
CS = LOW
U/D = 0
CLK
RWB
Figure 3. Decrement RWB
04419-0-006
1
0
1
0
1
0
CS
CLK
U/D
RWB
tS
tUDS
tCL
tCH
tCSS
tCSH
Figure 4. Detailed Timing Diagram (Only RWB Decrement Shown)
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| AD5227BUJZ50-RL72 | 制造商:AD 制造商全稱:Analog Devices 功能描述:64-Position Up/Down Control Digital Potentiometer |
| AD5227EVAL | 制造商:AD 制造商全稱:Analog Devices 功能描述:64-Position Up/Down Control Digital Potentiometer |
| AD5228 | 制造商:AD 制造商全稱:Analog Devices 功能描述:32-Position Manual Up/Down Control Potentiometer |
| AD5228BUJZ10 | 制造商:Analog Devices 功能描述:DGTL POTENTIOMETER 32POS 10KOHM SGL 8PIN TSOT - Bulk |
| AD5228BUJZ100 | 制造商:Analog Devices 功能描述:DGTL POTENTIOMETER 32POS 100KOHM SGL 8PIN TSOT - Bulk |
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