參數(shù)資料
型號: AD5235BRU25
廠商: ANALOG DEVICES INC
元件分類: 數(shù)字電位計(jì)
英文描述: RES MF 1/8W 160K 1% 2PPM
中文描述: DUAL 25K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 1024 POSITIONS, PDSO16
封裝: MO-153AB, TSSOP-16
文件頁數(shù): 3/10頁
文件大?。?/td> 102K
代理商: AD5235BRU25
PRELIMINARY TECHNICAL DATA
Nonvolatile Memory Digital Potentiometers
ELECTRICAL CHARACTERISTICS 25K, 250K OHM VERSIONS
(V
DD
= +3V±10% to +5V±10% and V
SS
=0V, V
A
= +V
DD
, V
B
= 0V, -40°C < T
A
< +85°C unless otherwise noted.)
Parameter
Symbol
Conditions
AD5235
REV PrD 6 NOV, 2000
Information contained in this Product Concept data sheet describes a product in the early definition stage. There is no guarantee that the
information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara,
CA. TEL(408)562-7254; FAX (408)727-1550; walt.heinzer@analog.com
3
Min
Typ
1
Max
Units
INTERFACE TIMING CHARACTERISTICS applies to all parts(Notes 5, 8)
Clock Cycle Time
Input Clock Pulse Width
CS
Setup Time
Data Setup Time
Data Hold Time
CLK Shutdown Time
CS
Rise to Clock Rise Setup
CS
High Pulse Width
CLK to SDO Propagation Delay
9
Store to Nonvolatile EEMEMSave Time
10
t
11
CS
to SDO - SPI line acquire
CS
to SDO - SPI line release
RDY Rise to CLK Rise
Startup Time
CLK Setup Time
Preset Pulse Width
t
1
t
2
, t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
Clock level high or low
FromPositive CLK transition
FromPositive CLK transition
R
L
= 1K
, C
L
< 20pF
Applies to Command 2
H
, 3
H
For 1 CLK period (t
4
- t
3
= 1 CLK period)
20
10
10
5
5
0
10
10
1
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ms
ns
ns
25
25
t
12
t
13
t
14
t
15
t
16
t
PR
NOTES:
1.
2.
Typicals represent average readings at +25°C and V
DD
= +5V.
Resistor position nonlinearity error R-INL is the deviation froman ideal value measured between the maximumresistance and the mnimumresistance wiper positions. R-DNL measures the relative step
change fromideal between successive tap positions. Parts are guaranteed monotonic. See figure 20 test circuit. I
W
= V
DD
/R for both V
DD
=+3V or V
DD
=+5V.
INL and DNL are measured at V
W
with the RDAC configured as a potentiometer divider simlar to a voltage output D/A converter. V
A
= V
DD
and V
B
= 0V.
DNL specification limts of ±1LSB maximumare Guaranteed Monotonic operating conditions. See Figure 19 test circuit.
Resistor termnals A,B,W have no limtations on polarity with respect to each other.
Guaranteed by design and not subject to production test.
P
DISS
is calculated from(I
DD
x V
DD
=+5V).
All dynamc characteristics use V
DD
= +5V.
See timng diagramfor location of measured values. All input control voltages are specified with t
R
=t
F
=2.5ns(10% to 90% of 3V) and timed froma voltage level of 1.5V. Switching characteristics are
measured using both V
DD
= +3V or +5V.
Propagation delay depends on value of V
DD
, R
PULL_UP
, and C
L
see applications text.
Low only for commands 8, 9,10, 2, 3: CMD_8 ~ 1ms; CMD_9,10 ~0.1ms; CMD_2,3 ~20ms.
3.
4.
5.
6.
7.
8.
9.
10.
Timing Diagram
t
2
t
3
MSB
LSB
MSB
LSB
CLK
CS
SDI
SDO
1
t
1
t
4
t
5
t
6
t
7
t
9
t
13
t
10
RDY
t
11
t
16
MSB
LSB
SDO
2
t
12
t
14
t
15
SDO
1
CLK IDLES LOW
Figure 1. Timing Diagram
SDO
2
CLK IDLES HIGH
t
8
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