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參數(shù)資料
| 型號(hào)： | AD5235BRU25 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字電位計(jì) |
| 英文描述： | RES MF 1/8W 160K 1% 2PPM |
| 中文描述： | DUAL 25K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 1024 POSITIONS, PDSO16 |
| 封裝： | MO-153AB, TSSOP-16 |
| 文件頁數(shù)： | 6/10頁 |
| 文件大?。?/td> | 102K |
| 代理商： | AD5235BRU25 |
PRELIMINARY TECHNICAL DATA
Nonvolatile Memory Digital Potentiometers
AD5235
REV PrD 6 NOV, 2000
Information contained in this Product Concept data sheet describes a product in the early definition stage. There is no guarantee that the
information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara,
CA. TEL(408)562-7254; FAX (408)727-1550; walt.heinzer@analog.com
6
Table 2. AD5235 Instruction/Operation Truth Table
Inst
No.
B15 B8
C3 C2 C1 C0 A3 A2 A1 A0
0
0 0 0 0 X X X X
Instruction Byte 1
Data Byte 1
B15
B8
X D9 D8 D7 D0
X X X
Data Byte 0
B7 B0
Operation
NOP: Do nothing
X X
1
0 0 0 1 << ADDR >>
X X X
X X
Write contents of EEMEM(ADDR) to RDAC(ADDR)
Register
SAVE WIPER SETTING: Write contents of
RDAC(ADDR) to EEMEM(ADDR)
Write contents of Serial Register Data Byte 0 & 1 to
EEMEM(ADDR)
DEC 6dB: Right Shift contents of RDAC(ADDR) ,
LSB rolls over to MSB position
DEC All 6dB: Right Shift contents of all RDAC
Registers, LSB rolls over to MSB position
Decrement contents of RDAC(ADDR) by One, does
not rollover at zero-scale
Decrement contents of all RDAC Registers by One,
does not rollover at zero-scale
RESET: Load all RDACs with their
corresponding
EEMEMpreviously-saved values
Write contents of EEMEM(ADDR) to Serial Register
Data Byte 0 & 1
Write contents of RDAC(ADDR) to Serial Register
Data Byte 0 & 1
Write contents of Serial Register Data Byte 0 &1 to
RDAC(ADDR)
INC 6dB: Left Shift contents of RDAC(ADDR), stops
at all 'Ones'.
INC All 6dB: Right Shift contents of all RDAC
Registers, stops at all 'Ones'.
Increment contents of RDAC(ADDR) by One, does
not rollover at full-scale stops at all 'Ones'.
Increment contents of all RDAC Registers by One,
does not rollover at full-scale stops at all 'Ones'.
2
0 0 1 0 << ADDR >>
X X X
X X
3
0 0 1 1 << ADDR >>
X D9 D8 D7 D0
4
0 1 0 0 << ADDR >>
X X X
X X
5
0 1 0 1 X X X X
X X X
X X
6
0 1 1 0 << ADDR >>
X X X
X X
7
0 1 1 1 X X X X
X X X
X X
8
1 0 0 0 0 0 0 0
X X X
X X
9
1 0 0 1 << ADDR >>
X X X
X X
10
1 0 1 0 << ADDR >>
X X X
X X
11
1 0 1 1 << ADDR >>
X D9 D8 D7 D0
12
1 1 0 0 << ADDR >>
X X X
X X
13
1 1 0 1 X X X X
X X X
X X
14
1 1 1 0 << ADDR >>
X X X
X X
15
1 1 1 1 X X X X
X X X
X X
NOTES:
1. The SDO output shifts-out the last 24-bits of data clocked into the serial register for daisy chain operation. Exception,
following Instruction #9 or #10 the selected internal register data will be present in data byte 0 & 1. Instructions following
#9 & #10 must be a full 24-bit data word to completely clock out the contents of the serial register.
2. The RDAC register is a volatile scratch pad register that is refreshed at power ON from the corresponding non-volatile
EEMEM register.
3. The increment, decrement and shift commands ignore the contents of the shift register Data Byte 0.
4. Execution of the Operation column noted in the table takes place when the
CS
strobe returns to logic high.
.
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