t8 t1
參數(shù)資料
型號: AD5242BRU1M
廠商: Analog Devices Inc
文件頁數(shù): 16/20頁
文件大?。?/td> 0K
描述: IC DGTL POT 256POS 16-TSSOP
標(biāo)準(zhǔn)包裝: 96
接片: 256
電阻(歐姆): 1M
電路數(shù): 2
溫度系數(shù): 標(biāo)準(zhǔn)值 30 ppm/°C
存儲器類型: 易失
接口: I²C(設(shè)備位址)
電源電壓: 2.7 V ~ 5.5 V,±2.3 V ~ 2.7 V
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 16-TSSOP
包裝: 管件
配用: EVAL-AD5242EBZ-ND - BOARD EVALUATION FOR AD5242
AD5241/AD5242
Rev. C | Page 5 of 20
TIMING DIAGRAMS
t8
t1
t8
t3
t2
t9
t5
SDA
SCL
t10
S
P
t7
t4
S
P
t6
0
926
-00
5
Figure 3. Detail Timing Diagram
Data of AD5241/AD5242 is accepted from the I2C bus in the following serial format.
Table 2.
S
0
1
0
1
AD1
AD0
R/W
A
A/B
RS
SD
O1
O2
X
A
D7
D6
D5
D4
D3
D2
D1
D0
A
P
Slave Address Byte
Instruction Byte
Data Byte
where:
S = start condition
P = stop condition
A = acknowledge
X = don’t care
AD1, AD0 = Package pin programmable address bits. Must be matched with the logic states at Pins AD1 and AD0.
R/W = Read enable at high and output to SDA. Write enable at low.
A/B = RDAC subaddress select; 0 for RDAC1 and 1 for RDAC2.
RS = Midscale reset, active high.
SD = Shutdown in active high. Same as SHDN except inverse logic.
O1, O2 = Output logic pin latched values
D7, D6, D5, D4, D3, D2, D1, D0 = data bits.
1
9
0
1
0
1
A/B
D0
D4
D5
D6
D7
D3
D2
D1
ACK BY
AD5241
ACK BY
AD5241
ACK BY
AD5241
STOP BY
MASTER
START BY
MASTER
FRAME 1
SLAVE ADDRESS BYTE
FRAME 2
INSTRUCTION BYTE
FRAME 3
DATA BYTE
SDA
1
AD1
AD0
R/W
SCL
X
2
1
SD
RS
00
92
6-
0
06
O
Figure 4. Writing to the RDAC Serial Register
1
9
1
9
0
1
0
11
D7
ACK BY
AD5241
NO ACK BY
MASTER
STOP BY
MASTER
START BY
MASTER
FRAME 1
SLAVE ADDRESS BYTE
FRAME 2
DATA BYTE FROM PREVIOUSLY SELECTED
RDAC REGISTER IN WRITE MODE
SCL
SDA
D6
D5
D4
D3
D2
D1
D0
AD1
AD0
R/W
0
09
26
-00
7
Figure 5. Reading Data from a Previously Selected RDAC Register in Write Mode
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