W
參數(shù)資料
型號: AD5242BRU1M
廠商: Analog Devices Inc
文件頁數(shù): 18/20頁
文件大?。?/td> 0K
描述: IC DGTL POT 256POS 16-TSSOP
標(biāo)準(zhǔn)包裝: 96
接片: 256
電阻(歐姆): 1M
電路數(shù): 2
溫度系數(shù): 標(biāo)準(zhǔn)值 30 ppm/°C
存儲器類型: 易失
接口: I²C(設(shè)備位址)
電源電壓: 2.7 V ~ 5.5 V,±2.3 V ~ 2.7 V
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 16-TSSOP
包裝: 管件
配用: EVAL-AD5242EBZ-ND - BOARD EVALUATION FOR AD5242
AD5241/AD5242
Rev. C | Page 7 of 20
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
TOP VIEW
(Not to Scale)
14
1
NC = NO CONNECT
W1
B1
VDD
SHDN
SCL
SDA
O1
NC
O2
VSS
DGND
AD1
AD0
A1
AD5241
2
3
4
5
6
7
13
12
11
10
9
8
00
92
6-
00
3
Figure 6. AD5241 Pin Configuration
TOP VIEW
(Not to Scale)
1
O1
A1
W1
B1
VDD
SHDN
SCL
SDA
A2
W2
B2
O2
VSS
DGND
AD1
AD0
AD5242
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
00
92
6-
00
4
Figure 7. AD5242 Pin Configuration
Table 4. AD5241 Pin Function Descriptions
Pin No.
Mnemonic
Description
1
A1
Resistor Terminal A1.
2
W1
Wiper Terminal W1.
3
B1
Resistor Terminal B1.
4
VDD
Positive Power Supply, Specified for
Operation from 2.2 V to 5.5 V.
5
SHDN
Active low, asynchronous connection of
Wiper W to Terminal B, and open circuit
of Terminal A. RDAC register contents
unchanged. SHDN should tie to VDD
if not used.
6
SCL
Serial Clock Input.
7
SDA
Serial Data Input/Output.
8
AD0
Programmable Address Bit for Multiple
Package Decoding. Bit AD0 and Bit AD1
provide four possible addresses.
9
AD1
Programmable Address Bit for Multiple
Package Decoding. Bit AD0 and Bit AD1
provide four possible addresses.
10
DGND
Common Ground.
11
VSS
Negative Power Supply, Specified for
Operation from 0 V to 2.7 V.
12
O2
Logic Output Terminal O2.
13
NC
No Connect.
14
O1
Logic Output Terminal O1.
Table 5. AD5242 Pin Function Descriptions
Pin No.
Mnemonic
Description
1
O1
Logic Output Terminal O1.
2
A1
Resistor Terminal A1.
3
W1
Wiper Terminal W1.
4
B1
Resistor Terminal B1.
5
VDD
Positive Power Supply, Specified for
Operation from 2.2 V to 5.5 V.
6
SHDN
Active Low, Asynchronous Connection
of Wiper W to Terminal B, and Open
Circuit of Terminal A. RDAC register
contents unchanged. SHDN should
tie to VDD, if not used.
7
SCL
Serial Clock Input.
8
SDA
Serial Data Input/Output.
9
AD0
Programmable Address Bit for Multiple
Package Decoding. Bit AD0 and Bit AD1
provide four possible addresses.
10
AD1
Programmable Address Bit for Multiple
Package Decoding. Bit AD0 and Bit AD1
provide four possible addresses.
11
DGND
Common Ground.
12
VSS
Negative Power Supply, Specified for
Operation from 0 V to 2.7 V.
13
O2
Logic Output Terminal O2.
14
B2
Resistor Terminal B2.
15
W2
Wiper Terminal W2.
16
A2
Resistor Terminal A2.
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