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參數(shù)資料
| 型號： | SC16C650BIB48,128 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 9/48頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC UART SOT313-2 |
| 標(biāo)準包裝： | 2,000 |
| 通道數(shù)： | 1，UART |
| FIFO's： | 32 字節(jié) |
| 電源電壓： | 2.5V，3.3V，5V |
| 帶自動流量控制功能： | 是 |
| 帶IrDA 編碼器/解碼器： | 是 |
| 帶故障啟動位檢測功能： | 是 |
| 帶調(diào)制解調(diào)器控制功能： | 是 |
| 帶CMOS： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 935274391128 SC16C650BIB48-F SC16C650BIB48-F-ND |
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SC16C650B_4
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 14 September 2009
17 of 48
NXP Semiconductors
SC16C650B
UART with 32-byte FIFOs and IrDA encoder/decoder
[6]
This bit controls the OUT pin in the HVQFN32 package, and OUT1 in the other packages.
[7]
The Special register set is accessible only when LCR[7] is set to a logic 1.
[8]
Enhanced Feature Register (EFR), Xon1, Xon2 Xoff1, Xoff2 are accessible only when LCR is set to BFh.
7.1 Transmit Holding Register (THR) and Receive Holding Register (RHR)
The serial transmitter section consists of an 8-bit Transmit Holding Register (THR) and
Transmit Shift Register (TSR). The status of the THR is provided in the Line Status
Register (LSR). Writing to the THR transfers the contents of the data bus (D[7:0]) to the
THR, providing that the THR or TSR is empty. The THR empty ag in the LSR register will
be set to a logic 1 when the transmitter is empty or when data is transferred to the TSR.
Note that a write operation can be performed when the THR empty ag is set
(logic 0 = FIFO full; logic 1 = at least one FIFO location available).
The serial receive section also contains an 8-bit Receive Holding Register (RHR).
Receive data is removed from the SC16C650B and receive FIFO by reading the RHR
register. The receive section provides a mechanism to prevent false starts. On the falling
edge of a start or false start bit, an internal receiver counter starts counting clocks at the
16
× clock rate. After 71
2 clocks, the start bit time should be shifted to the center of the
start bit. At this time the start bit is sampled, and if it is still a logic 0 it is validated.
Evaluating the start bit in this manner prevents the receiver from assembling a false
character. Receiver status codes will be posted in the LSR.
7.2 Interrupt Enable Register (IER)
The Interrupt Enable Register (IER) masks the interrupts from receiver ready, transmitter
empty, line status and modem status registers. These interrupts would normally be seen
on the INT output pin.
Table 9.
Interrupt Enable Register bits description
Bit
Symbol
Description
7
IER[7]
CTS interrupt.
logic 0 = disable the CTS interrupt (normal default condition)
logic 1 = enable the CTS interrupt. The SC16C650B issues an interrupt when
the CTS pin transitions from a logic 0 to a logic 1.
6
IER[6]
RTS interrupt.
logic 0 = disable the RTS interrupt (normal default condition)
logic 1 = enable the RTS interrupt. The SC16C650B issues an interrupt when
the RTS pin transitions from a logic 0 to a logic 1.
5
IER[5]
Xoff interrupt.
logic 0 = disable the software ow control, receive Xoff interrupt (normal
default condition).
logic 1 = enable the software ow control, receive Xoff interrupt. See Section
6.4 “Software ow control” for details.
4
IER[4]
Sleep mode.
logic 0 = disable Sleep mode (normal default condition)
logic 1 = enable Sleep mode. See Section 6.9 “Sleep mode” for details.
3
IER[3]
Modem Status Interrupt.
logic 0 = disable the modem status register interrupt (normal default
condition)
logic 1 = enable the modem status register interrupt
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