參數(shù)資料
型號: SC16C650BIB48,128
廠商: NXP Semiconductors
文件頁數(shù): 45/48頁
文件大?。?/td> 0K
描述: IC UART SOT313-2
標準包裝: 2,000
通道數(shù): 1,UART
FIFO's: 32 字節(jié)
電源電壓: 2.5V,3.3V,5V
帶自動流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動位檢測功能:
帶調制解調器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應商設備封裝: 48-LQFP(7x7)
包裝: 帶卷 (TR)
其它名稱: 935274391128
SC16C650BIB48-F
SC16C650BIB48-F-ND
SC16C650B_4
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 14 September 2009
6 of 48
NXP Semiconductors
SC16C650B
UART with 32-byte FIFOs and IrDA encoder/decoder
D0
2
43
28
I/O
Data bus. Eight data lines with 3-state outputs provide a
bidirectional path for data, control and status information between
the UART and the CPU.
D1
3
44
29
I/O
D2
4
45
30
I/O
D3
5
46
31
I/O
D4
6
47
32
I/O
D5
7
2
1
I/O
D6
8
3
2
I/O
D7
9
4
3
I/O
DCD
42
40
-
I
Data carrier detect. DCD is a modem status signal. Its condition
can be checked by reading MSR[7] (DCD). MSR[3] (
DCD)
indicates that DCD has changed states since the last read from the
MSR. If the modem status interrupt is enabled when DCD changes
levels, an interrupt is generated.
DDIS
26
22
-
O
Driver disable. DDIS is active (LOW) when the CPU is reading
data. When inactive (HIGH), DDIS can disable an external
transceiver.
DSR
41
39
26
I
Data set ready. DSR is a modem status signal. Its condition can be
checked by reading MSR[5] (DSR). MSR[1] (
DSR) indicates DSR
has changed levels since the last read from the MSR. If the modem
status interrupt is enabled when DSR changes levels, an interrupt is
generated.
DTR
37
33
22
O
Data terminal ready. When active (LOW), DTR informs a modem
or data set that the UART is ready to establish communication. DTR
is placed in the active level by setting the DTR bit of the Modem
Control Register. DTR is placed in the inactive level either as a
result of a Master Reset, during loopback mode operation, or
clearing the DTR bit.
INT
33
30
20
O
Interrupt. When active (HIGH), INT informs the CPU that the UART
has an interrupt to be serviced. Four conditions that cause an
interrupt to be issued are: a receiver error, received data that is
available or timed out (FIFO mode only), an empty transmitter
holding register or an enabled modem status interrupt. INT is reset
(deactivated) either when the interrupt is serviced or as a result of a
Master Reset.
OUT1
38
34
-
O
Outputs 1 and 2. These are user-designated output terminals that
are set to the active (low) level by setting respective Modem Control
Register (MCR) bits (OUT1 and OUT2). OUT1 and OUT2 are set to
the inactive (HIGH) level as a result of Master Reset, during
loopback mode operations, or by clearing bit 2 (OUT1) or bit 3
(OUT2) of the MCR.
OUT2
35
31
-
O
OUT
-
23
O
RCLK
10
5
4
I
Receiver clock. RCLK is the 16
× baud rate clock for the receiver
section of the UART.
IOR
25
20
-
I
Read inputs. When either IOR or IOR is active (LOW or HIGH,
respectively) while the UART is selected, the CPU is allowed to
read status information or data from a selected UART register. Only
one of these inputs is required for the transfer of data during a read
operation; the other input should be tied to its inactive level (i.e.,
IOR tied LOW or IOR tied HIGH).
IOR
24
19
14
I
Table 2.
Pin description …continued
Symbol
Pin
Type
Description
PLCC44
LQFP48 HVQFN32
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