參數(shù)資料
型號(hào)： AD5252BRU50-RL7
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字電位計(jì)
英文描述： 32-Tap. Nonvolatile. Linear-Taper Digital Potentiometers in SOT23
中文描述： DUAL 50K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO14
封裝： MO-153AB-1, TSSOP-14
文件頁(yè)數(shù)： 11/28頁(yè)
文件大?。?/td> 859K
代理商： AD5252BRU50-RL7
AD5251/AD5252
I
2
C INTERFACE DETAIL DESCRIPTION
Rev. 0 | Page 11 of 28
0 WRITE
0
S
0
1
0
1
1
A
D
1
A
D
0
0
A
A
4
A
3
A
2
A
1
A
0
A
P
DATA
0
(1 BYTE +
ACKNOWLEDGE)
SLAVE ADDRESS
INSTRUCTIONS
AND ADDRESS
CMD/
REG
EE/
RDAC
0 REG
A/
A
FROM MASTER TO SLAVE
FROM SLAVE TO MASTER
S = START CONDITION
P = STOP CONDITION
A = ACKNOWLEDGE (SDA LOW)
A = NOT ACKNOWLEDGE (SDA HIGH)
R/W = READ ENABLE AT HIGH AND WRITE ENABLE AT LOW
CMD/REG = COMMAND ENABLE BIT, LOGIC HIGH/REGISTER ACCESS BIT, LOGIC LOW
EE/RDAC = EEMEM REGISTER, LOGIC HIGH/RDAC REGISTER, LOGIC LOW
A4, A3, A2, A1, A0
= RDAC/EEMEM REGISTER ADDRESSES
Figure 7. Single Write Mode
0 WRITE
0
S
0
1
0
1
1
A
D
1
A
D
0
0
A
A
4
A
3
A
2
A
1
A
0
P
A
A
RDAC1
DATA
RDAC3
DATA
0
(N BYTES +
ACKNOWLEDGE)
RDAC SLAVE ADDRESS
RDAC INSTRUCTIONS
AND ADDRESS
CMD/
REG
EE/
RDAC
0 REG
A/
A
Figure 8. Consecutive Write Mode
Table 6. Addresses for Writing Data Byte Contents to RDAC Registers (R/W = 0, CMD/REG = 0, EE/RDAC = 0)
A4
A3
A2
A1
A0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
0
0
1
0
0
:
:
:
:
:
0
1
1
1
1
RDAC
Reserved
RDAC1
Reserved
RDAC3
Reserved
Reserved
Data Byte Description
6- or 8 bit wiper setting (2 MSBs of AD5251 are X)
6- or 8 bit wiper setting (2 MSBs of AD5251 are X)
RDAC/EEMEM WRITE
Setting the wiper position requires an RDAC write operation.
The single write operation is shown in Figure 7, and the
consecutive write operation is shown in Figure 8. In the
consecutive write operation, if the RDAC is selected and the
address starts at 00001, the first data byte goes to RDAC1 and
the second data byte goes to RDAC3. The RDAC address is
shown in Table 6.
While the RDAC wiper setting is controlled by a specific RDAC
register, each RDAC register corresponds to a specific EEMEM
location, which provides nonvolatile wiper storage functionality.
The addresses are shown in Table 7. The single and consecutive
write operations apply also to EEMEM write operations.
There are 12 nonvolatile memory locations: EEMEM4 to
EEMEM15. Users can store a total of 12 bytes of information,
such as memory data for other components, look-up tables, or
system identification information.
In a write operation to the EEMEM registers, the device disables
the I
2
C interface during the internal write cycle. Acknowledge
polling is required to determine the completion of the write
cycle. See EEMEM Write-Acknowledge Polling.
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