參數(shù)資料
型號(hào)： AD5252BRU50-RL7
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字電位計(jì)
英文描述： 32-Tap. Nonvolatile. Linear-Taper Digital Potentiometers in SOT23
中文描述： DUAL 50K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO14
封裝： MO-153AB-1, TSSOP-14
文件頁(yè)數(shù)： 7/28頁(yè)
文件大?。?/td> 859K
代理商： AD5252BRU50-RL7
AD5251/AD5252
INTERFACE TIMING CHARACTERISTICS
Guaranteed by design, not subject to production test. See Figure 3 for location of measured values. All input control voltages are
specified with tR = tF = 2.5 ns (10% to 90% of 3 V), and timed from a voltage level of 1.5 V. Switching characteristics are measured
using both V
DD
= 3 V and 5 V.
Table 3. Interface Timing and EEMEM Reliability Characteristics (All Parts).
Parameter
Symbol
Conditions
INTERFACE TIMING
SCL Clock Frequency
f
SCL
tBUF Bus Free Time between STOP and
START
t
HD;STA
Hold Time (Repeated START)
t
2
After this period, the first clock pulse
is generated
t
LOW
Low Period of SCL Clock
t
3
t
HIGH
High Period of SCL Clock
t
4
t
SU;STA
Setup Time For START Condition
t
5
t
HD;DAT
Data Hold Time
t
6
t
SU;DAT
Data Setup Time
t
7
t
F
Fall Time of Both SDA and SCL Signals
t
8
t
R
Rise Time of Both SDA and SCL Signals
t
9
t
SU;STO
Setup Time for STOP Condition
t
10
EEMEM Data Storing Time
t
EEMEM_STORE
EEMEM Data Restoring Time at
Power-On
1
without decoupling capacitors at V
DD
and V
SS
.
EEMEM Data Restoring Time Upon
Restore Command or RESET Operation
1
EEMEM Rewritable Time (delay time after
Power On or RESET before EEMEM can
be written)
Rev. 0 | Page 7 of 28
Min
1.3
Typ
Max
400
Unit
kHz
μs
t
1
0.6
μs
1.3
0.6
0.6
0
100
0.6
26
300
0.9
300
300
μs
μs
μs
μs
ns
ns
ns
μs
ms
μs
t
EEMEM_RESTORE1
V
DD
rise time dependent. Measure
t
EEMEM_RESTORE2
V
DD
= 5 V
300
μs
t
EEMEM_REWRITE
540
μs
FLASH/EE MEMORY RELIABILITY
Endurance
2
Data Retention
3
100
100
kCycles
Years
1
During power-up, all outputs preset to midscale before restoring to the final EEMEM contents. RDAC0 has the shortest, whereas RDAC3 has the longest EEMEM data
restoring time.
2
Retention lifetime equivalent at junction temperature T
J
= 55°C per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6 eV derates
with junction temperature.
3
When the part is not in operation, the SDA and SCL pins should be pulled to high. When these pins are pulled to low, the I
2
C interface at these pins conducts current of
about 0.8 mA at V
DD
= 5.5 V and 0.2 mA at V
DD
= 2.7 V.
相關(guān)PDF資料
PDF描述
AD5251BRU1-RL7 Memory Card Socket; No. of Contacts:50; Leaded Process Compatible:Yes; Mounting Type:Surface Mount; Peak Reflow Compatible (260 C):Yes; Gender:Male; No. of Rows:1; Width:31.60mm RoHS Compliant: Yes
AD5251EVAL Memory Card Socket; No. of Contacts:50; Leaded Process Compatible:Yes; Mounting Type:Surface Mount; Peak Reflow Compatible (260 C):Yes; Gender:Male; No. of Rows:1; Width:31.60mm RoHS Compliant: Yes
AD5252EVAL 32-Tap. Nonvolatile. Linear-Taper Digital Potentiometers in SOT23
AD5253EVAL Dual, 256-Tap, Nonvolatile, I2C-Interface, Digital Potentiometers
AD5254BRU1 Dual, 256-Tap, Nonvolatile, I2C-Interface, Digital Potentiometers
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