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參數(shù)資料
| 型號： | AD5254BRU100-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 15/32頁 |
| 文件大小： | 0K |
| 描述： | IC DGTL POT QUAD 100K 20-TSSOP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 接片： | 256 |
| 電阻（歐姆）： | 100k |
| 電路數(shù)： | 4 |
| 溫度系數(shù)： | 標(biāo)準(zhǔn)值 650 ppm/°C |
| 存儲器類型： | 非易失 |
| 接口： | I²C（設(shè)備位址） |
| 電源電壓： | 2.7 V ~ 5.5 V，±2.25 V ~ 2.75 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-TSSOP |
| 包裝： | 帶卷 (TR) |
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AD5253/AD5254
Data Sheet
Rev. C | Page 22 of 32
DIGITAL INPUT/OUTPUT CONFIGURATION
SDA is a digital input/output with an open-drain MOSFET that
requires a pull-up resistor for proper communication. On the
other hand, SCL and WP are digital inputs for which pull-up
resistors are recommended to minimize the MOSFET cross-
conduction current when the driving signals are lower than
VDD. SCL and WP have ESD protection diodes, as shown in
WP can be permanently tied to VDD without a pull-up resistor if
the write-protect feature is not used. If WP is left floating, an
internal current source pulls it low to enable write protection. In
applications in which the device is programmed infrequently,
this allows the part to default to write-protection mode after
any one-time factory programming or field calibration without
using an on-board pull-down resistor. Because there are
protection diodes on all inputs, the signal levels must not be
greater than VDD to prevent forward biasing of the diodes.
03824-0-035
GND
SCL
VDD
Figure 35. SCL Digital Input
03824-0-036
GND
INPUTS
WP
VDD
Figure 36. Equivalent WP Digital Input
MULTIPLE DEVICES ON ONE BUS
The AD5253/AD5254 are equipped with two addressing pins,
AD1 and AD0, that allow up to four AD5253/AD5254 devices
to be operated on one I2C bus. To achieve this result, the states of
AD1 and AD0 on each device must first be defined. An example
device is issued a different slave address—01011(AD1)(AD0)—
to complete the addressing.
Table 12. Multiple Devices Addressing
AD1
AD0
Device Addressed
0
U1
0
1
U2
1
0
U3
1
U4
SDA
AD1
AD0
MASTER
SCL
SDA
AD1
AD0
SCL
SDA
AD1
AD0
SCL
SDA
5V
RP
5V
AD1
AD0
SCL
AD5253/
AD5254
AD5253/
AD5254
AD5253/
AD5254
AD5253/
AD5254
03824-0-037
Figure 37. Multiple AD5253/AD5254 Devices on a Single Bus
In wireless base station smart-antenna systems that require
arrays of digital potentiometers to bias the power amplifiers,
large numbers of AD5253/AD5254 devices can be addressed by
using extra decoders, switches, and I/O buses, as shown in
Figure 38. For example, to communicate to a total of 16 devices,
four decoders and 16 sets of combinational switches (four sets
shown in Figure 38) are needed. Two I/O buses serve as the
common inputs of the four 2 × 4 decoders and select four sets
of outputs at each combination. Because the four sets of
combination switch outputs are unique, as shown in Figure 38,
a specific device is addressed by properly programming the I2C
with the slave address defined as 01011(AD1)(AD0). This
operation allows one of 16 devices to be addressed, provided
that the inputs of the two decoders do not change states. The
inputs of the decoders are allowed to change once the operation
of the specified device is completed.
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