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參數(shù)資料
| 型號(hào)： | AD5258EVAL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD5258 DGTL POT |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 數(shù)字電位器 |
| 已用 IC / 零件： | AD5258 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | AD5258BRMZ1-ND - IC POT DGTL I2C1K 64P 10MSOP AD5258BRMZ10-ND - IC POT DGTL I2C 10K 64P 10MSOP AD5258BRMZ100-ND - IC POT DGTL I2C 100K 64P 10MSOP AD5258BRMZ50-ND - IC POT DGTL I2C 50K 64P 10MSOP AD5258BRMZ1-R7-ND - IC POT DGTL I2C 1K 64P 10MSOP AD5258BRMZ10-R7-ND - IC POT DGTL I2C 10K 64P 10MSOP AD5258BRMZ50-R7-ND - IC POT DGTL I2C 50K 64P 10MSOP AD5258BRMZ100-R7-ND - IC POT DGTL I2C 100K 64P 10MSOP |
Data Sheet
AD5258
Rev. D | Page 19 of 24
ESD PROTECTION OF DIGITAL PINS AND
RESISTOR TERMINALS
The AD5258 VDD, VLOGIC, and GND power supplies define the
boundary conditions for proper 3-terminal and digital input
operation. Supply signals present on Terminal A, Terminal B,
and Terminal W that exceed VDD or GND are clamped by the
internal forward-biased ESD protection diodes (see Figure 40).
Digital Input SCL and Digital Input SDA are clamped by ESD
protection diodes with respect to VLOGIC and GND as shown in
GND
A
W
B
VDD
05029-
041
Figure 40. Maximum Terminal Voltages Set by VDD and GND
05029-
042
GND
SCL
SDA
VLOGIC
Figure 41. Maximum Terminal Voltages Set by VLOGIC and GND
POWER-UP SEQUENCE
Because the ESD protection diodes limit the voltage compliance
at Terminal A, Terminal B, and Terminal W (see Figure 40), it is
important to power GND/VDD/VLOGIC before applying any volt-
age to Terminal A, Terminal B, and Terminal W; otherwise, the
diode is forward-biased such that VDD and VLOGIC are powered
unintentionally and may affect the user’s circuit. The ideal
power-up sequence is in the following order: GND, VDD,
VLOGIC, digital inputs, and then VA, VB, VW. The relative order
of powering VA, VB, VW and the digital inputs is not important
as long as they are powered after GND, VDD, and VLOGIC.
LAYOUT AND POWER SUPPLY BYPASSING
It is good practice to employ compact, minimum lead length
layout design. The leads to the inputs should be as direct as
possible with minimum conductor length. Ground paths
should have low resistance and low inductance.
Similarly, it is also good practice to bypass the power supplies
with quality capacitors for optimum stability. Supply leads to
the device should be bypassed with disc or chip ceramic capaci-
tors of 0.01 F to 0.1 F. In addition, low ESR 1 F to 10 F
tantalum or electrolytic capacitors should be applied at the
supplies to minimize any transient disturbance and low fre-
quency ripple (see Figure 42). As well, the digital ground
should be joined remotely to the analog ground at one point
to minimize the ground bounce.
VDD
GND
VDD
C2
10F
C1
0.1F
AD5258
+
05029-
043
Figure 42. Power Supply Bypassing
MULTIPLE DEVICES ON ONE BUS
The AD5258 has two configurable address pins, AD0 and AD1.
The state of these two pins is registered upon power-up and
decoded into a corresponding I2C-compatible 7-bit address (see
Table 5). This allows up to four devices on the bus to be written
to or read from independently.
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