參數(shù)資料
型號(hào)： AD5271BRMZ-100
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 10/24頁(yè)
文件大?。?/td> 0K
描述： IC RHEOSTAT 5V 50-TP 256 10MSOP
標(biāo)準(zhǔn)包裝： 50
接片： 256
電阻（歐姆）： 100k
電路數(shù)： 1
溫度系數(shù)： 標(biāo)準(zhǔn)值 5 ppm/°C
存儲(chǔ)器類型： 非易失
接口： 4 線串行
電源電壓： 2.7 V ~ 5.5 V，±2.5 V ~ 2.75 V
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 10-TFSOP，10-MSOP（0.118"，3.00mm 寬）
供應(yīng)商設(shè)備封裝： 10-MSOP
包裝： 管件
AD5270/AD5271
Data Sheet
Rev. F | Page 18 of 24
THEORY OF OPERATION
The AD5270 and AD5271 are designed to operate as true
variable resistors for analog signals within the terminal voltage
range of VSS < VTERM < VDD. The RDAC register contents deter-
mine the resistor wiper position. The RDAC register acts as a
scratchpad register, which allows unlimited changes of resistance
settings. The RDAC register can be programmed with any position
setting using the SPI interface. When a desirable wiper position
is found, this value can be stored in a 50-TP memory register.
Thereafter, the wiper position is always restored to that position
for subsequent power-up. The storing of 50-TP data takes approx-
imately 350 ms; during this time, the AD5270/AD5271 lock to
prevent any changes from taking place.
The AD5270/AD5271 also feature a patented 1% end-to-end
resistor tolerance. This simplifies precision, rheostat mode, and
open-loop applications where knowledge of absolute resistance
is critical.
SERIAL DATA INTERFACE
The AD5270/AD5271 contain a serial interface (SYNC, SCLK,
DIN , and SDO), which is compatible with SPI interface standards,
as well as most DSPs. This device allows writing of data via the
serial interface to every register.
SHIFT REGISTER
For the AD5270/AD5271, the shift register is 16 bits wide, as
shown in Figure 2. The 16-bit word consists of two unused bits,
which should be set to zero, followed by four control bits and
10 RDAC data bits (note that for the AD5271 only, the lower
two RDAC data bits are don’t care if the RDAC register is read
from or written to). Data is loaded MSB first (Bit 15). The four
control bits determine the function of the software command as
listed in Table 11. Figure 3 shows a timing diagram of a typical
AD5270/AD5271 write sequence.
The write sequence begins by bringing the SYNC line low. The
SYNC pin must be held low until the complete data-word is
loaded from the DIN pin. When SYNC returns high, the serial
data-word is decoded according to the instructions in Table 11.
The command bits (Cx) control the operation of the digital
potentiometer. The data bits (Dx) are the values that are loaded
into the decoded register. The AD5270/AD5271 have an internal
counter that counts a multiple of 16 bits (a frame) for proper
operation. For example, AD5270/AD5271 each works with a
32-bit word but do not work properly with a 31-bit or 33-bit
word. The AD5270/AD5271 do not require a continuous SCLK
when SYNC is high. To minimize power consumption in the
digital input buffers, operate all serial interface pins close to the
VDD supply rails.
RDAC REGISTER
The RDAC register directly controls the position of the digital
rheostat wiper. For example, when the RDAC register is loaded
with all zeros, the wiper is connected to Terminal A of the variable
resistor. The RDAC register is a standard logic register and
there is no restriction on the number of changes allowed. The
basic mode of setting the variable resistor wiper position
(programming the RDAC register) is accomplished by loading
the serial data input register with Command 1 (see Table 11) and
with the desired wiper position data.
50-TP MEMORY BLOCK
The AD5270/AD5271 contain an array of 50-TP programmable
memory registers, which allow the wiper position to be pro-
grammed up to 50 times. Table 13 shows the memory map.
When the desired wiper position is determined, the user can
load the serial data input register with Command 3 (see Table 11)
which stores the wiper position data in a 50-TP memory
register. The first address to be programmed is Location 0x01
(see Table 13); the AD5270/AD5271 increments the 50-TP
memory address for each subsequent program until the memory
is full. Programming data to 50-TP consumes approximately
4 mA for 55 ms, and takes approximately 350 ms to complete,
during which time the shift register locks to prevent any changes
from occurring. Bit C3 of the control register can be polled to
verify that the fuse program command was completed properly.
No change in supply voltage is required to program the 50-TP
memory; however, a 1 μF capacitor on the EXT_CAP pin is
required (see Figure 46). Prior to 50-TP activation, the AD5270
and the AD5271 preset to midscale on power up.
WRITE PROTECTION
At power-up, the serial data input register write commands for
both the RDAC register and the 50-TP memory registers are
disabled. The RDAC write protect bit, C1, of the control register
(see Table 13 and Table 14) is set to 0 by default. This disables
any change of the RDAC register content regardless of the
software commands, except that the RDAC register can be
refreshed from the 50-TP memory using the software reset,
Command 4. To enable programming of the RDAC register, the
write protect bit (Bit C1), of the control register must first be
programmed by loading the serial data input register with
Command 7. To enable programming of the 50-TP memory,
the program enable bit (Bit C0) of the control register, which is
set to 0 by default, must first be set to 1.
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