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參數(shù)資料
| 型號(hào)： | AD5271BRMZ-100 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 2/24頁 |
| 文件大小： | 0K |
| 描述： | IC RHEOSTAT 5V 50-TP 256 10MSOP |
| 標(biāo)準(zhǔn)包裝： | 50 |
| 接片： | 256 |
| 電阻（歐姆）： | 100k |
| 電路數(shù)： | 1 |
| 溫度系數(shù)： | 標(biāo)準(zhǔn)值 5 ppm/°C |
| 存儲(chǔ)器類型： | 非易失 |
| 接口： | 4 線串行 |
| 電源電壓： | 2.7 V ~ 5.5 V，±2.5 V ~ 2.75 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-MSOP |
| 包裝： | 管件 |
AD5270/AD5271
Data Sheet
Rev. F | Page 10 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VDD 11
VSS
2
A
3
W
4
SDO
10
9
8
SCLK
7
5
EXT_CAP
DIN
6
GND
AD5270/
AD5271
TOP VIEW
(Not to Scale)
SYNC
08
077
-00
5
Figure 5. MSOP Pin Configuration
SYNC
VDD 1
VSS
2
A
3
W
4
SDO
10
9
8
SCLK
7
5
EXT_CAP
DIN
6 GND
NOTES
1. THE EXPOSED PAD IS LEFT FLOATING
OR IS TIED TO VSS.
AD5270/
AD5271
(EXPOSED
PAD)
08
07
7-
0
40
Figure 6. LFCSP Pin Configuration
Table 10. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
VDD
Positive Power Supply. Decouple this pin with 0.1 μF ceramic capacitors and 10 μF capacitors.
2
A
Terminal A of RDAC. VSS ≤ VA ≤ VDD.
3
W
Wiper Terminal of RDAC. VSS ≤ VW ≤ VDD.
4
VSS
Negative Supply. Connect to 0 V for single-supply applications. Decouple this pin with 0.1 μF ceramic
capacitors and 10 μF capacitors.
5
EXT_CAP
External Capacitor. Connect a 1 μF capacitor between EXT_CAP and VSS. This capacitor must have a voltage
rating of ≥7 V.
6
GND
Ground Pin, Logic Ground Reference.
7
SDO
Serial Data Output. This pin can be used to clock data from the shift register in daisy-chain mode or in
readback mode. This open-drain output requires an external pull-up resistor even if it is not use.
8
DIN
Serial Data Line. This pin is used in conjunction with the SCLK line to clock data into or out of the 16-bit input
register.
9
SCLK
Serial Clock Input. Data is clocked into the shift register on the falling edge of the serial clock input. Data can
be transferred at rates up to 50 MHz.
10
SYNC
Falling Edge Synchronization Signal. This is the frame synchronization signal for the input data. When SYNC
goes low, it enables the shift register and data is transferred in on the falling edges of the subsequent clocks.
The selected register is updated on the rising edge of SYNC following the 16th clock cycle. If SYNC is taken
high before the 16th clock cycle, the rising edge of SYNC acts as an interrupt, and the write sequence is
ignored by the RDAC.
EPAD
Exposed Pad
Leave floating or connected to VSS.
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