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| 型號： | AD5274BRMZ-20-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 16/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DGTL POT 20K 256POS 10MSOP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 接片： | 256 |
| 電阻（歐姆）： | 20k |
| 電路數(shù)： | 1 |
| 溫度系數(shù)： | 標(biāo)準(zhǔn)值 5 ppm/°C |
| 存儲器類型： | 非易失 |
| 接口： | I²C |
| 電源電壓： | 2.7 V ~ 5.5 V，±2.5 V ~ 2.75 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-MSOP |
| 包裝： | 帶卷 (TR) |
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Data Sheet
AD5272/AD5274
Rev. D | Page 23 of 28
50-TP MEMORY WRITE-ACKNOWLEDGE POLLING
After each write operation to the 50-TP registers, an internal
write cycle begins. The I2C interface of the device is disabled.
To determine if the internal write cycle is complete and the
I2C interface is enabled, interface polling can be executed. I2C
interface polling can be conducted by sending a start condition,
followed by the slave address and the write bit. If the I2C interface
responds with an acknowledge (ACK), the write cycle is complete
and the interface is ready to proceed with further operations.
Otherwise, I2C interface polling can be repeated until it completes.
RESET
The AD5272/AD5274 can be reset through software by executing
Command 4 (see Table 12) or through hardware on the low
pulse of the RESET pin. The reset command loads the RDAC
register with the contents of the most recently programmed 50-TP
memory location. The RDAC register loads with midscale if no
50-TP memory location has been previously programmed. Tie
RESET to VDD if the RESET pin is not used.
RESISTOR PERFORMANCE MODE
This mode activates a new, patented 1% end-to-end resistor
tolerance that ensures a ±1% resistor tolerance on each code,
resistor tolerance. The resistor performance mode is activated by
programming Bit C2 of the control register (see Table 14 and
SHUTDOWN MODE
The AD5272/AD5274 can be shut down by executing the software
shutdown command, Command 9 (see Table 12), and setting
the LSB to 1. This feature places the RDAC in a zero-power-
consumption state where Terminal Ax is disconnected from
the wiper terminal. It is possible to execute any command from
Table 12 while the AD5272 or AD5274 is in shutdown mode.
The part can be taken out of shutdown mode by executing
Command 9 and setting the LSB to 0, or by issuing a software
or hardware reset.
RDAC ARCHITECTURE
To achieve optimum performance, Analog Devices has patented the
RDAC segmentation architecture for all the digital potentiometers.
In particular, the AD5272/AD5274 employ a three-stage
segmentation approach, as shown in Figure 46. The AD5272/
AD5274 wiper switch is designed with the transmission gate
CMOS topology.
A
W
10-/8-BIT
ADDRESS
DECODER
RL
RM
RW
SW
RW
08076-
008
Figure 46. Simplified RDAC Circuit
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation—1% Resistor Tolerance
The nominal resistance between Terminal W and Terminal A, RWA,
is available in 20 k, 50 k, and 100 k, and 1024-/256-tap points
accessed by the wiper terminal. The 10-/8-bit data in the RDAC
latch is decoded to select one of the 1024 or 256 possible wiper
settings. The AD5272/ AD5274 contain an internal ±1% resistor
tolerance calibration feature which can be disabled or enabled,
enabled by default, or by programming Bit C2 of the control
register (see Table 15). The digitally programmed output resis-
tance between the W terminal and the A terminal, RWA, is
calibrated to give a maximum of ±1% absolute resistance error
over both the full supply and temperature ranges. As a result,
the general equations for determining the digitally programmed
output resistance between the W terminal and A terminal are as
follows:
For the AD5272
WA
R
D
R
×
=
1024
)
(
(1)
For the AD5274
WA
R
D
R
×
=
256
)
(
(2)
where:
D is the decimal equivalent of the binary code loaded in the
10-/8-bit RDAC register.
RWA is the end-to-end resistance.
In the zero-scale condition, a finite total wiper resistance of
120 is present. Regardless of which setting the part is oper-
ating in, take care to limit the current between the A terminal
to B terminal, W terminal to A terminal, and W terminal to
B terminal, to the maximum continuous current of ±3 mA, or
the pulse current specified in Table 8. Otherwise, degradation or
possible destruction of the internal switch contact can occur.
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