VDD = 2." />
參數(shù)資料
型號(hào)： AD5274BRMZ-20-RL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 26/28頁(yè)
文件大?。?/td> 0K
描述： IC DGTL POT 20K 256POS 10MSOP
標(biāo)準(zhǔn)包裝： 1,000
接片： 256
電阻（歐姆）： 20k
電路數(shù)： 1
溫度系數(shù)： 標(biāo)準(zhǔn)值 5 ppm/°C
存儲(chǔ)器類(lèi)型： 非易失
接口： I²C
電源電壓： 2.7 V ~ 5.5 V，±2.5 V ~ 2.75 V
工作溫度： -40°C ~ 125°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 10-TFSOP，10-MSOP（0.118"，3.00mm 寬）
供應(yīng)商設(shè)備封裝： 10-MSOP
包裝： 帶卷 (TR)
Data Sheet
AD5272/AD5274
Rev. D | Page 7 of 28
INTERFACE TIMING SPECIFICATIONS
VDD = 2.5 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 7.
Limit at TMIN, TMAX
Parameter
Conditions1
Min
Max
Unit
Description
Standard mode
100
kHz
Serial clock frequency
Fast mode
400
kHz
Serial clock frequency
t1
Standard mode
4
s
tHIGH, SCL high time
Fast mode
0.6
s
tHIGH, SCL high time
t2
Standard mode
4.7
s
tLOW, SCL low time
Fast mode
1.3
s
tLOW, SCL low time
t3
Standard mode
250
ns
tSU;DAT, data setup time
Fast mode
100
ns
tSU;DAT, data setup time
t4
Standard mode
0
3.45
s
tHD;DAT, data hold time
Fast mode
0
0.9
s
tHD;DAT, data hold time
t5
Standard mode
4.7
s
tSU;STA, set-up time for a repeated start condition
Fast mode
0.6
s
tSU;STA, set-up time for a repeated start condition
t6
Standard mode
4
s
tHD;STA, hold time (repeated) start condition
Fast mode
0.6
s
tHD;STA, hold time (repeated) start condition
High speed mode
160
ns
tHD;STA, hold time (repeated) start condition
t7
Standard mode
4.7
s
tBUF, bus free time between a stop and a start condition
Fast mode
1.3
s
tBUF, bus free time between a stop and a start condition
t8
Standard mode
4
s
tSU;STO, setup time for a stop condition
Fast mode
0.6
s
tSU;STO, setup time for a stop condition
t9
Standard mode
1000
ns
tRDA, rise time of SDA signal
Fast mode
300
ns
tRDA, rise time of SDA signal
t10
Standard mode
300
ns
tFDA, fall time of SDA signal
Fast mode
300
ns
tFDA, fall time of SDA signal
t11
Standard mode
1000
ns
tRCL, rise time of SCL signal
Fast mode
300
ns
tRCL, rise time of SCL signal
t11A
Standard mode
1000
ns
tRCL1, rise time of SCL signal after a repeated start condition and
after an acknowledge bit
Fast mode
300
ns
tRCL1, rise time of SCL signal after a repeated start condition and
after an acknowledge bit
t12
Standard mode
300
ns
tFCL, fall time of SCL signal
Fast mode
300
ns
tFCL, fall time of SCL signal
t13
RESET pulse time
20
ns
Minimum RESET low time
tSP3
Fast mode
0
50
ns
Pulse width of spike suppressed
500
ns
Command execute time
tRDAC_R-PERF
2
s
RDAC register write command execute time (R-Perf mode)
tRDAC_NORMAL
600
ns
RDAC register write command execute time (normal mode)
tMEMORY_READ
6
s
Memory readback execute time
tMEMORY_PROGRAM
350
ms
Memory program time
tRESET
600
s
Reset 50-TP restore time
t
POWER-UP
2
ms
Power-on 50-TP restore time
1
Maximum bus capacitance is limited to 400 pF.
2
The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate but has a negative effect on EMC behavior
of the part.
3
Input filtering on the SCL and SDA inputs suppress noise spikes that are less than 50 ns for fast mode.
4
Refer to tRDAC_R-PERF and tRDAC_NORMAL for RDAC register write operations.
5
Refer to t
MEMORY_READ
and tMEMORY_PROGRAM for memory commands operations.
6
Maximum time after VDD VSS is equal to 2.5 V.
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