參數(shù)資料
型號: AD5325BRMZ
廠商: Analog Devices Inc
文件頁數(shù): 12/24頁
文件大小: 0K
描述: IC DAC 12BIT 2WIRE I2C 10-MSOP
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝: 50
設(shè)置時間: 6µs
位數(shù): 12
數(shù)據(jù)接口: I²C,串行
轉(zhuǎn)換器數(shù)目: 4
電壓電源: 單電源
功率耗散(最大): 5mW
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 10-TFSOP,10-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 10-MSOP
包裝: 管件
輸出數(shù)目和類型: 4 電壓,單極;4 電壓,雙極
采樣率(每秒): 125k
產(chǎn)品目錄頁面: 782 (CN2011-ZH PDF)
AD5305/AD5315/AD5325
Rev. G | Page 2 of 24
TABLE OF CONTENTS
REVISION HISTORY
5/06—Rev. F to Rev. G
Updated Format..................................................................Universal
Changes to Ordering Guide .......................................................... 24
10/04—Rev. E to Rev. F
Changes to Figure 6........................................................................ 11
Changes to Pointer Byte Bits Section ........................................... 12
Changes to Figure 7........................................................................ 12
8/03—Rev. D to Rev. E
Added A Version.................................................................Universal
Changes to Features.......................................................................... 1
Changes to Specifications ................................................................ 2
Changes to Absolute Maximum Ratings ....................................... 5
Changes to Ordering Guide ............................................................ 5
Changes to TPC 21......................................................................... 10
Added Octals Section to Table II.................................................. 18
Updated Outline Dimensions....................................................... 19
4/01—Rev. C to Rev. D
Edit to Features Section ....................................................................1
Edit to Figure 6 ..................................................................................1
Edits to Right/Left and Double Sections
of Pointer Byte Bits Section........................................................... 11
Edit to Input Shift Register Section.............................................. 12
Edit to Multiple-DAC Readback Sequence Section................... 12
Edits to Figure 7.............................................................................. 12
Edits to Write Operation section.................................................. 13
Edits to Figure 8.............................................................................. 13
Edits to Read Operation section................................................... 14
Edits to Figure 9.............................................................................. 14
Edits to Power-Down Modes section .......................................... 15
Edits to Figure 12............................................................................ 16
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